Scheme and method for testing analog-to digital converters
First Claim
1. A method for testing analog-to-digital converters, which comprises steps of:
- Inputting a test trig signal, a system clock pulse and a power source;
Integrating the clock signal regulated to be a step-ramp signal;
Inputting the step-ramp signal to the ADC under test;
Outputting digital output codes of the ADC under test and the reference counter;
Comparing the output codes of the ADC under test and the reference counter; and
Outputting the compared results.
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Abstract
The invention provides a test scheme of analog-to-digital converters and method thereof. It comprises: a control circuit, a step-ramp signal generator, a multiplexer, an n+m-bit counter, and a test analyzing circuit, wherein m=1, 2, 3 . . . , based on desired accuracy of the test scheme. A clock pulse is coupled to the n+m-bit counter and a control circuit for regulating duty cycle, amplitude, and frequency. It is also coupled to a step-ramp signal generating circuit for being integrated as a test signal source. Therefore the step-ramp signal can synchronize with the n+m-bit counter, and the output codes are applied to compare with output codes of the n-bit ADCs for completely digitally analyzing ADC'"'"'s parameters. The step-ramp signal is divided into several segments, each is integrated by the regulated clock signal with different duty cycles, which increases integrating time to compensate leakage currents of the capacitor and improve linearity of the step-ramp signal.
14 Citations
8 Claims
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1. A method for testing analog-to-digital converters, which comprises steps of:
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Inputting a test trig signal, a system clock pulse and a power source;
Integrating the clock signal regulated to be a step-ramp signal;
Inputting the step-ramp signal to the ADC under test;
Outputting digital output codes of the ADC under test and the reference counter;
Comparing the output codes of the ADC under test and the reference counter; and
Outputting the compared results. - View Dependent Claims (2, 3)
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4. A scheme for testing analog-to-digital converter, It comprises components of:
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A control circuit, which adjusts the frequency, amplitude, and duty cycle of a system clock pulse;
A test signal generator, which contains an integrator that receives the regulated clock signal of the control circuit to generate a step-ramp signal;
A multiplexer, which is controlled by the test trig signal to choose either normal signal or test stimulus;
An n-bit analog-to-digital converter under test;
An n+m-bit counter whose output codes is synchronous with the step-ramp signal plays as a reference signal generator when analyzing the parameters of the ADC under test; and
A test response analyzer, which analyzes the output codes of the n-bit ADC under test and the n+m-bit counter. - View Dependent Claims (5, 6, 7, 8)
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Specification
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- Resources
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Current AssigneeNational Cheng KUNG University (Government of The Republic of China)
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Original AssigneeNational Cheng KUNG University (Government of The Republic of China)
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InventorsWen, Yun-Che
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Granted Patent
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Time in Patent OfficeDays
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Field of Search
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US Class Current341/120
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CPC Class CodesH03M 1/109 for dc performance, i.e. st...H03M 1/1095 for ac performance, i.e. dy...H03M 1/12 Analogue/digital converters...
