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Method for reduced pitch lithography

DC CAFC
  • US 5,652,084 A
  • Filed: 10/22/1996
  • Issued: 07/29/1997
  • Est. Priority Date: 12/22/1994
  • Status: Expired due to Term
First Claim
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1. A lithography method for semiconductor fabrication using a semiconductor wafer, comprising the steps of:

  • (a) forming a first imaging layer over the semiconductor wafer;

    (b) patterning the first imaging layer in accordance with a first pattern to form a first patterned layer having a first feature;

    (c) stabilizing the first patterned layer;

    (d) forming a second imaging layer over the first pattern layer; and

    (e) patterning the second imaging layer in accordance with a second pattern to form a second patterned layer having a second feature distinct from the first feature, wherein the second patterned layer and the first patterned layer form a single patterned layer, and wherein the first and second features which are formed relatively closer to one another than is possible through a single exposure to radiation.

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