Memory devices with selectable access type and methods using the same
DCFirst Claim
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1. A memory comprising:
- an array of rows and columns of memory cells;
row decoder circuitry for selecting a said row in said array for access;
first column decoder circuitry for selecting a location within a first group of said columns along said selected row;
second column decoder circuitry for selecting for access a location within a second group of said columns along said selected row; and
control circuitry operable during a selected random cycle to initiate a page access through a selected one of said first and second column decoder circuitry and a random access through another one of said first and second column decoder circuitry.
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Abstract
A memory 200 including an array 201 of rows and columns of memory cells. Row decoder circuitry 211 is provided for selecting in response to a row address a row in array 201 for access. Column decoder circuitry 205 is provided for selecting at least one location within a first group of columns along the selected row in array 201 in response to a column address. At least one shift register 207 is provided for allowing serial access to one of the cells within a second group of columns along the selected row.
39 Citations
32 Claims
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1. A memory comprising:
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an array of rows and columns of memory cells; row decoder circuitry for selecting a said row in said array for access; first column decoder circuitry for selecting a location within a first group of said columns along said selected row; second column decoder circuitry for selecting for access a location within a second group of said columns along said selected row; and control circuitry operable during a selected random cycle to initiate a page access through a selected one of said first and second column decoder circuitry and a random access through another one of said first and second column decoder circuitry. - View Dependent Claims (2, 3, 6, 7)
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4. A memory comprising:
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an array of rows and columns of memory cells; row decoder circuitry for selecting a selected row in said array for access; first column decoder circuitry for selecting a location within a first group of said columns along said selected row in; second column decoder circuitry for selecting for access a location within a second group of said columns along said selected row; control circuitry for selectively performing an access of a selected type to a selected said location of a selected one said first and second groups of columns through said first and second column decoder circuitry; and at least one shift register coupled to a third group of said columns for providing serial access to cells within said third group of columns along said selected row. - View Dependent Claims (5, 11)
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8. A memory comprising:
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an array of rows and columns of memory cells, said array of cells comprising first and second subarrays each comprising selected ones of said rows; row decoder circuitry for selecting a selected row in said array for access; first column decoder circuitry for selecting a location within a first group of said columns along said selected row in; second column decoder circuitry for selecting for access a location within a second group of said columns along said selected row; and control circuitry for selectively performing an access of a selected type to a selected said location of a selected one said first and second groups of columns through said first and second column decoder circuitry. - View Dependent Claims (9, 10)
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12. A memory comprising:
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an array of rows and columns of memory cells; row decoder circuitry for selecting in response to a row address a row in said array for access; column decoder circuitry for selecting at least one location within a first group of columns along said selected row in said array in response to a column address; and at least one shift register for providing serial access to ones of said cells within a second group of columns along said selected row. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
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24. A processing system comprising:
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a central processing unit; a bus coupled to said central processing unit; core logic coupled to said bus; and a memory coupled to said core logic comprising; an array of memory cells arranged in rows and columns; means for selecting a selected row in said array for access; means for selectively performing random and page mode accesses to said cells of said selected row and first selected ones of said columns; and means for selectively performing serial accesses to cells of said selected row and second selected ones of said columns. - View Dependent Claims (25, 26, 27)
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28. A method of performing different accesses during a single RAS cycle to a memory array of rows and columns of memory cells, the columns of cells including a plurality of separately addressable groups, the method comprising the steps of:
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selecting a row in the array for access; selecting a first type of access to be made to a first selected one of the groups of columns; performing the selected type of access to the first selected group of columns; selecting a second type of access to be made to a second selected one of the groups of columns, the second type of access differing from the first type of access; and performing the selected type of access to the second selected group of columns. - View Dependent Claims (29)
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30. The method of Column 28 wherein said steps of performing are performed substantially simultaneously.
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31. A method of performing multiple types of accesses during a single RAS cycle to a memory including an array of rows and columns of memory cells, column decoder circuitry for selecting at least one location within a first group of columns, and at least one shift register for providing serial access to a second group of columns, the method comprising the steps of:
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selecting a row in the array for access; providing at least one address to the column decoder to select at least one column of the first group for access; accessing at least one corresponding cell along the selected row and the selected column of the first group, the access of a type selected from random and page mode accesses; and serially accessing data to at least one cell along the selected row corresponding to at least one column in the second group. - View Dependent Claims (32)
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Specification