Synchronous memory device having dual input registers of pipeline structure in data path

The present invention discloses a synchronous memory device capable of processing data at a high speed in a read path of the memory device, by decreasing the timing margin of the external clock signal which is input into the input registers, of the pipeline structure the memory device comprises: a) an address pad receiving an address signal; b) a first input register coupled to the address pad, wherein the first input registers including:, 1) a first switching device coupled to the address pad, wherein the first switching device is controlled by a first control signal; 2) a first latch device for storing the address signal from the first switching device; and 3) a second switching device coupled to the first latch device, wherein the second switching device is controlled by a second control signal, and wherein-the second control signal is 180° out of phase from the first control signal; c) a second input register coupled to the first input register in parallel, wherein the second input,registers including: 1) a third switching device coupled to the address pad, wherein the third switching device is controlled by the second control signal; 2) a second latch device for storing the address signal from the third switching device; and 3) a fourth switching device coupled to the second latch device, wherein the fourth switching device is controlled by the first; d) an inverting device for output from the second switching device; and e) a decoding means for decoding the output from the inverting means.