Video and/or audio decompression and/or compression device that shares a memory interface
DC CAFCFirst Claim
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1. An electronic system coupled to a memory, comprising:
- a first device that requires access to the memory;
a decoder that requires access to the memory sufficient to maintain real time operation; and
a memory interface for coupling to the memory, and coupled to the first device and to the decoder, the memory interface having an arbiter for selectively providing access for the first device and the decoder to the memory and a shared bus coupled to the memory the first device, and the decoder, the bus having a sufficient bandwidth to enable the decoder to access the memory and operate in real time when the first device simultaneously accesses the bus.
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Abstract
An electronic system that contains a first device that requires a memory interface and video and/or audio decompression and/or compression device that shares a memory interface and memory with the first device while still permitting the video and/or audio decompression and/or compression device to operate in real time is disclosed.
158 Citations
33 Claims
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1. An electronic system coupled to a memory, comprising:
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a first device that requires access to the memory; a decoder that requires access to the memory sufficient to maintain real time operation; and a memory interface for coupling to the memory, and coupled to the first device and to the decoder, the memory interface having an arbiter for selectively providing access for the first device and the decoder to the memory and a shared bus coupled to the memory the first device, and the decoder, the bus having a sufficient bandwidth to enable the decoder to access the memory and operate in real time when the first device simultaneously accesses the bus. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A computer comprising:
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processing means; an input device connected to the processing means; an output device connected to the processing means; a memory connected to the processing means; a first device that requires access to the memory; a decoder that requires access to the memory sufficient to maintain real time operation; and a memory interface coupled to the memory, to the first device, and to the decoder, the memory interface having a means for selectively providing access for the first device and the decoder to the memory and a shared bus coupled to the decoder, the first device, and the memory, the shared bus having a sufficient bandwidth to enable the decoder to operate in real time while sharing access to the bus. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28)
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29. In an electronic system having a first device coupled to a memory interface and a memory coupled to the memory interface, the first device having a device priority and capable of generating a request to access the memory, a method for selectively providing access to the memory comprising the steps of:
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providing a decoder coupled to the memory interface through a bus having sufficient bandwidth to enable the decoder to operate in real time while sharing access to the bus, having a decoder priority and capable of generating a request to access the memory; providing an arbiter having an idle, a busy and a queue state; generating a request by the decoder to access the memory; determining the state of the arbiter; providing the decoder access to the memory responsive to the arbiter being in the idle state for the decoder to operate in real time; queuing the request responsive to the arbiter being in the busy state; and queuing the request responsive to the arbiter being in the queue state in an order responsive to the priority of the decoder request and the priority of any other queued requests. - View Dependent Claims (30, 31, 32, 33)
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Specification