System and method for sending multiple data signals over a serial link

DC CAFC

US 5,835,498 A
Filed: 06/14/1996
Issued: 11/10/1998
Est. Priority Date: 10/05/1995
Status: Expired due to Term

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1. An apparatus for transmitting a plurality of data streams as a single data stream, the apparatus comprising:

an encoder having a plurality of inputs and a plurality of outputs, each of the plurality of inputs coupled to receive a respective data stream, the encoder producing encoded data words from the data streams,a multiplexor having a control input, a plurality of data inputs and an output, the multiplexor selecting one of the plurality of inputs to be output as a data transfer stream, the inputs of the multiplexor coupled to the plurality of outputs of the encoders;

a control code generator for producing other control codes identifying streams and idle conditions and isochronous control codes, the control code generator having a plurality of outputs coupled to corresponding inputs of the multiplexor; and

a scheduler having a plurality of inputs and an output, the scheduler controlling the data stream output by the multiplexor, the plurality of inputs of the scheduler coupled to the plurality of outputs of the encoder, and the output of the scheduler coupled to the control input of the multiplexor.

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Abstract

A system and method for sending multiple data signals over a serial link comprises an embedding unit and a removing unit coupled by a serial line. The embedding unit preferably receives a plurality of data streams, encodes the data streams and then merges the encoded data into a serial stream that is output across a serial line to the removing unit. The removing unit receives a serial stream of data, decodes the serial stream, and then separates the decoded serial stream into separate streams thereby reconstructing the streams input to the embedding unit. The encoding and transmission by the embedding unit and the receipt and decoding by the removing unit are completely transparent, the signals output by the removing unit are identical in timing and data content to the signals input to the embedding unit. The present invention also includes a method for transmitting a plurality of data streams over a signal line, and a method for generating a plurality of data streams from a serial sequence.

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1. An apparatus for transmitting a plurality of data streams as a single data stream, the apparatus comprising:
- an encoder having a plurality of inputs and a plurality of outputs, each of the plurality of inputs coupled to receive a respective data stream, the encoder producing encoded data words from the data streams,a multiplexor having a control input, a plurality of data inputs and an output, the multiplexor selecting one of the plurality of inputs to be output as a data transfer stream, the inputs of the multiplexor coupled to the plurality of outputs of the encoders;
  
  a control code generator for producing other control codes identifying streams and idle conditions and isochronous control codes, the control code generator having a plurality of outputs coupled to corresponding inputs of the multiplexor; and
  
  a scheduler having a plurality of inputs and an output, the scheduler controlling the data stream output by the multiplexor, the plurality of inputs of the scheduler coupled to the plurality of outputs of the encoder, and the output of the scheduler coupled to the control input of the multiplexor.
- View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
- - 2. The apparatus of claim 1, further comprising a parallel-to-serial converter having an input and an output, the input of the parallel-to-serial converter coupled to the output of the multiplexor receive an n-bit word in parallel, the parallel-to-serial converter outputting the n-bit word as a serial stream.
  - 3. The apparatus of claim 1, further comprising a data buffer having a plurality of inputs and a plurality of outputs, the data buffer coupled between the encoder and the multiplexor.
  - 4. The apparatus of claim 3, wherein the data buffer comprises a plurality of dedicated buffers, each of the dedicated buffers having an input and an output, each of the dedicated buffers having storing an encoded data stream output by the encoder, and each of the dedicated buffers coupled between a respective one of the plurality of outputs of the encoder and a respective one of the plurality of inputs of the multiplexor.
  - 5. The apparatus of claim 1, wherein the control code generator is a plurality of lines wired to word values assigned for other control codes and isochronous control codes.
  - 6. The apparatus of claim 1, wherein each of the inputs of the encoder receives eight bits in parallel and each output of the encoder provides 10 bits in parallel, and the encoder encodes each group of eight bits into a group of ten bits.
  - 7. The apparatus of claim 1, wherein the encoder further comprises a plurality of dedicated encoders, each of the dedicated encoders having an input and an output, the input of each dedicated encoder coupled to receive a respective data stream, and the output of each dedicated encoder coupled to a respective input of the multiplexor.
  - 8. The apparatus of claim 7, wherein the each of the dedicated encoder encodes one from the group of data signals and control signals.
  - 9. The apparatus of claim 7, wherein the at least one of the plurality of dedicated encoders encodes a combination of data signals and control signals.
  - 10. The apparatus of claim 7, wherein a first one of the plurality of dedicated encoders encodes video data, a second one of the plurality of dedicated encoders encodes video control data, and a third one of the plurality of dedicated encoders encodes a first stream of data.
  - 11. The apparatus of claim 7, further comprising a plurality of dedicated buffers, each of the dedicated buffers having an input and an output, the input of each dedicated buffer coupled to an output of a respective dedicated encoder, and the outputs of each dedicated buffer coupled to inputs of the multiplexor.
  - 12. The apparatus of claim 1, wherein the scheduler is state machine formed from combinational logic that determines whether the encoder has data to be transmitted, and generates signals to control the multiplexor to output data and control codes such that isochronous control codes have the highest priority and are transmitted before other data streams, and transmission of other data streams is preceded by a stream start control code.
  - 13. The apparatus of claim 1, wherein the scheduler further comprises:
    - means for determining whether the encoder has data that is ready to be transmitted, the determining means coupled to the encoder; and
      
      means for identifying a stream that has data for transmission, the means for identifying coupled to the encoder;
      
      means for generating a first control signal for controlling the multiplexor to output a code identifying a beginning of a data stream transmission by the identified stream; and
      
      means for generating a second control signal for controlling the multiplexor to output the data from the encoder for the identified stream.

14. An apparatus for receiving a data stream and generating a plurality of data streams the apparatus comprising:
- a de-multiplexor having a control input, a plurality of data inputs and a first and second plurality of outputs, each of the first and second plurality of outputs providing a different stream of data, the plurality of data inputs of the de-multiplexor coupled to receive a data stream having a plurality of data words;
  
  a stream selector for generating a control signal indicating an output of the de-multiplexor to which to send a data word, comprising;
  
  a plurality of comparators, each comparator having a first input, a second input and an output, the first input of each comparator coupled to receive the data word from a converter and the second input of each comparator coupled to receive a respective stream start control word, and the outputs of the plurality of comparators coupled to control the de-multiplexor;
  
  a decoder having a plurality of inputs and a plurality of outputs for decoding data words the plurality of inputs of the decoder coupled to respective one of the plurality of outputs of the de-multiplexor; and
  
  an isochronous decoder having an inputs and a plurality of outputs for decoding isochronous control codes into timing control signals the input of the isochronous decoder coupled to the data input of the de-multiplexor.
- View Dependent Claims (15, 16, 17, 18)
- - 15. The apparatus of claim 14 wherein the converter further comprises an input and a plurality of outputs for converting a serial stream into the data stream having a plurality of data words output in parallel, the input of the converter coupled to a serial link, the plurality of outputs of the converter coupled to the plurality of input of the de-multiplexor, the apparatus further comprising:
    - a word aligner having a plurality of inputs and a plurality of outputs, the word aligner coupled between the converter and the de-multiplexor, the word aligner using idle words in the data stream and shifting the data bit-wise for word alignment.
  - 16. The apparatus of claim 15 wherein the word aligner further comprises:
    - a register having an input and an output, the input of the register coupled to the output of the converter, the register for storing a plurality of data words;
      
      a shifter having a data input, a control input and an output, the data input of the shifter coupled to the output of the register, the shifter outputting a predefined number of bits, the predefined number of bits less than a number of bits received at the input of the shifter; and
      
      an idle character detector having an input and an output, the input of the idle character detector coupled to the output of the register, and the output of the idle character detector coupled to the control input of the shifter, the idle character detector detecting an idle character and producing signals specifying the number of bits to shift a signal input to the shifter.
  - 17. The apparatus of claim 16 wherein the register further comprises:
    - a first register having an input and an output, the input of the first register coupled to the output of the converter, the output of the first register coupled to the idle character detector and the shifter;
      
      a second register having an input and an output, the input of the second register coupled to the output of the first register, the output of the second register coupled to the idle character detector and the shifter; and
      
      a third register having an input and an output, the input of the third register coupled to the output of the second register, the output of the third register coupled to the idle character detector and the shifter.
  - 18. The apparatus of claim 16 wherein the idle character detector further comprises:
    - an array of exclusive-OR gates having inputs and outputs, the inputs of the array of exclusive-OR gates coupled to the output of the register;
      
      a ones counter having inputs and outputs, the inputs of the ones counter coupled to the outputs of the array of exclusive-OR gates; and
      
      a control pointer register having a control input coupled by a register and combinational logic to the output of the ones counter to load the control pointer register with a value identifying the beginning of the word.

19. An apparatus for receiving a data stream and generating a plurality of data streams, the apparatus comprising:
- a de-multiplexor having a control input, a plurality of data inputs and a first and second plurality of outputs, each of the first and second plurality of outputs providing a different stream of data, the plurality of data inputs of the de-multiplexor coupled to receive a data stream having a plurality of data words;
  
  a stream selector having an input and an output for generating a control signal indicating an output of the de-multiplexor to which to send a data word, the input of the stream selector coupled to the data input of the de-multiplexor, and the output of the stream selector coupled to the control input of the de-multiplexor;
  
  a decoder having a plurality of inputs and a plurality of outputs for decoding data words, the plurality of inputs of the decoder coupled to respective one of the plurality of outputs of the de-multiplexor;
  
  an isochronous decoder having an inputs and a plurality of outputs for decoding isochronous control codes into timing control signals, the input of the isochronous decoder coupled to the data input of the de-multiplexor; and
  
  an n-stage bubble buffer for storing data words, the n-stage bubble buffer having an input and a first data output, and a second data output, the second data output of the n-stage bubble buffer coupled to the de-multiplexor, the input of the n-stage bubble buffer coupled to receive a data stream, the n-stage bubble buffer separating isochronous control codes from a data stream output to the de-multiplexor.
- View Dependent Claims (20)
- - 20. The apparatus of claim 19 wherein the n-stage bubble buffer further comprises:
    - a plurality of data buffers each having an input and an output, the plurality of data buffers coupled in a cascaded manner;
      
      a multiplexor having a plurality of data inputs, a control input and an output, the plurality of data inputs of the multiplexor each coupled to a respective output of one of the plurality of data buffers, the output of the multiplexor coupled to the input of the de-multiplexor; and
      
      a data selection controller having a plurality of inputs and an output, for generating a signal that selects one of the outputs of the plurality of data buffers for output by the multiplexor, the plurality of inputs of the data selection controller each coupled to a respective output of one of the plurality of data buffers, the output of the data selection controller coupled to the control input of the multiplexor, and one of the plurality of inputs of the data selection controller coupled to the output of the multiplexor.

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Current Assignee
Nexus Display Technologies LLC (Acacia Research Corporation)
Original Assignee
Silicon Image, Inc. (Lattice Semiconductor Corporation)
Inventors
Jeong, Deog-Kyoon, Kim, Sungjoon, Lee, David D.
Primary Examiner(s)
NGUYEN, CHAU T

Application Number

US08/664,136
Time in Patent Office

879 Days
Field of Search

370/526-528, 370/535-537, 370/509, 370/512, 370/470, 370/476, 370/522, 370/543, 370/465, 370/468, 370/542, 348/423, 348/430, 348/429, 348/432, 348/434, 348/385, 348/387, 348/388, 375/365-368
US Class Current

370/537
CPC Class Codes

G06F 13/4018   with data-width conversion

H03M 9/00   Parallel/series conversion ...

H04J 3/0605   Special codes used as synch...

H04L 2007/045   Fill bit or bits, idle words

H04L 25/085   Arrangements for reducing i...

H04L 25/4915   using pattern inversion or ...

H04L 7/0008   Synchronisation information...

H04L 7/0337   Selecting between two or mo...

H04N 21/23602   Multiplexing isochronously ...

H04N 21/4342   Demultiplexing isochronousl...

H04N 7/083   with signal insertion durin...

H04N 7/52   Systems for transmission of...

System and method for sending multiple data signals over a serial link

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Abstract

221 Citations

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System and method for sending multiple data signals over a serial link

First Claim

9 Assignments

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