Semiconductor memory device with redundancy circuit
DCFirst Claim
1. A semiconductor memory device comprising, a plurality of column selection lines, at least one redundant column selection line, a column decoder for activating one of said plurality of column selection lines in response to a column address, a first circuit generating a detection signal when the column address of a defective column selection line is supplied, and a second circuit activating said redundant column selection line in response to said detection signal and at least a part of said row address.
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Litigations
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Accused Products
Abstract
A semiconductor memory device which enhances the relief efficiency of defective bit lines by means of redundant bit lines is disclosed. To a column redundancy decoder are supplied not only a Y address but also a part of an X address. When a Y address corresponding to a defective bit line is supplied to the column redundancy decoder, the column redundancy decoder generates a detection signal. In this case, replacement by means of a redundant bit line is carried out if the part of the X address indicates a region where the defective bit line exists, and the replacement by means of a redundant bit line will not take place if it indicates a region where the defective bit line does not exists.
19 Citations
15 Claims
- 1. A semiconductor memory device comprising, a plurality of column selection lines, at least one redundant column selection line, a column decoder for activating one of said plurality of column selection lines in response to a column address, a first circuit generating a detection signal when the column address of a defective column selection line is supplied, and a second circuit activating said redundant column selection line in response to said detection signal and at least a part of said row address.
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6. A semiconductor memory device comprising:
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a plurality of word lines including at least first and second word lines; a plurality of bit lines including at least first and second bit lines; a plurality of redundant bit lines including at least first and second redundant bit lines; a plurality of memory cells each of which is disposed on intersections of said word lines and bit lines; a plurality of redundant memory cells each of which is disposed on intersections of said word lines and redundant bit lines; a plurality of column selection lines including at least a first column selection line;
said first and second bit lines being selected when said first column selection line is activated,a redundant column selection line;
said first and second redundant bit lines being selected when said redundant column selection line is activated,a column decoder activating said first column selection line in response to a first column address when said first word line is activated; and a column redundancy decoder activating said redundant column selection line in response to said first column address when said second word line is activated. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13, 14, 15)
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Specification