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Memory sharing architecture for a decoding in a computer system

DC
  • US 5,960,464 A
  • Filed: 08/23/1996
  • Issued: 09/28/1999
  • Est. Priority Date: 08/23/1996
  • Status: Expired due to Term
First Claim
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1. In a computer system having a main memory, a storage device having encoded data stored therein and a processor controlled by an operating system, an electronic device comprising:

  • a decoding circuit coupled to receive and decode the encoded data from the storage device; and

    a control circuit coupled to the decoding circuit, the processor and the main memory, the control circuit being configured to request continuous use of several portions of the main memory from the operating system, the portions of the main memory having noncontiguous addresses, and being configured to translate the noncontiguous addresses to contiguous addresses of a block of memory, andwherein the decoding circuit is configured to request at least some of the contiguous addresses of the block of memory, and wherein the control circuit translates the requested contiguous addresses of the block of memory to requested noncontiguous addresses and permits the decoding circuit to access the portions of the main memory.

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