Processing methods of forming contact openings and integrated circuitry
DC
First Claim
1. An integrated circuitry device comprising:
- a semiconductive substrate;
a field isolation oxide region received within the substrate and having a longitudinal axis;
a node location received within the substrate adjacent the field isolation oxide region and having a generally planar upper surface;
a layer of insulating material disposed over the substrate;
a contact opening to the node location received within the layer of insulating material, the contact opening having a top and a bottom within the layer of insulating material and a contact opening inner surface portion within the layer of insulating material which faces generally transversely away from the isolation oxide longitudinal axis and which extends between the top and bottom within the layer of insulating material, the contact opening inner surface portion joining with the generally planar upper surface of the node location and defining an angle with the node location generally planar upper surface which is greater at the contact opening bottom within the layer of insulating material than at the contact opening top within the layer of insulating material; and
conductive material disposed within the contact opening and forming an electrical connection with the node location.
1 Assignment
Litigations
1 Petition
Accused Products
Abstract
Methods of forming contact openings over a node location and related integrated circuitry are described. In one aspect of the invention, a node location is formed within a semiconductive substrate adjacent an isolation oxide region. A layer of material is formed over the node location and a contact opening is etched through the layer of material to outwardly expose a node location planar upper surface. In one preferred implementation, the contact opening includes an inner surface portion which faces generally transversely away from the isolation oxide region and which defines an angle with the node location upper surface which is greater at a bottom of the contact opening than at a top of the contact opening. In another preferred implementation, the contact opening includes sidewall portions which define a profile which having a non-uniform degree of taper between the contact opening top and bottom. In another preferred implementation, the tapering of the contact opening is effectuated by modifying at least one etching parameter at an intermediate etching point and continuing the etching to outwardly expose the node location.
10 Citations
7 Claims
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1. An integrated circuitry device comprising:
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a semiconductive substrate; a field isolation oxide region received within the substrate and having a longitudinal axis; a node location received within the substrate adjacent the field isolation oxide region and having a generally planar upper surface; a layer of insulating material disposed over the substrate; a contact opening to the node location received within the layer of insulating material, the contact opening having a top and a bottom within the layer of insulating material and a contact opening inner surface portion within the layer of insulating material which faces generally transversely away from the isolation oxide longitudinal axis and which extends between the top and bottom within the layer of insulating material, the contact opening inner surface portion joining with the generally planar upper surface of the node location and defining an angle with the node location generally planar upper surface which is greater at the contact opening bottom within the layer of insulating material than at the contact opening top within the layer of insulating material; and conductive material disposed within the contact opening and forming an electrical connection with the node location. - View Dependent Claims (2, 3, 4, 5)
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6. An integrated circuitry device comprising:
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a semiconductive substrate; a field isolation oxide region received within the substrate and having a longitudinal axis; a node location received within the substrate adjacent the field isolation oxide region and having a generally planar upper surface; a single layer of insulating material disposed over the substrate; a contact opening to the node location received within the single layer of insulating material, the contact opening having a top and a bottom within the single layer of insulating material and a contact opening inner surface portion within the single layer of insulating material which faces generally transversely away from the isolation oxide longitudinal axis and which extends between the top and bottom within the single layer of insulating material, the contact opening inner surface portion joining with the generally planar upper surface of the node location and defining an angle with the node location generally planar upper surface which is greater at the contact opening bottom within the single layer of insulating material than at the contact opening top within the single layer of insulating material; and conductive material disposed within the contact opening and forming an electrical connection with the node location, and wherein there is no conductive line disposed between the entirety of the conductive material within the contact opening and the field isolation oxide region. - View Dependent Claims (7)
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Specification
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- Resources
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Current AssigneeRound Rock Research LLC
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Original AssigneeMicron Technology, Inc.
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InventorsPrall, Kirk D., Donohoe, Kevin G.
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Primary Examiner(s)Arroyo, Teresa M.
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Assistant Examiner(s)DUONG, HUNG V
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Application NumberUS09/107,930Time in Patent Office504 DaysField of Search257/774, 257/758, 257/760, 257/308US Class Current257/774CPC Class CodesH01L 21/31116 by dry-etchingH01L 21/76804 by forming tapered via holes
