Microcomputer having variable bit width area for displacement and circuit for handling immediate data larger than instruction word
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First Claim
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1. A CPU capable of processing instructions in an instruction set and formed on a semiconductor chip, comprising:
- said instructions having an instruction length of each of the instructions to be processed by said CPU in said instruction set being of a first bit length;
an instruction register coupled to an instruction memory storing said instructions to be processed by said CPU in said instruction set, wherein a one instruction fetched in the instruction register has a displacement value;
decode means being supplied with said one instruction fetched in said instruction register and decoding said one instruction supplied from said instruction register;
an execution unit performing an operation of data,wherein the maximum data word length of said data to be processed by said execution unit is a second bit length;
a program counter storing an address of said one instruction fetched to said instruction register; and
wherein data stored in an address which is indicated by adding the address stored in said program counter to the displacement value is provided to said execution unit when the execution unit performs an operation for immediate data having a bit length of greater than said first bit length; and
,wherein said instruction set has at least one conditional branch instruction and at least one unconditional branch instruction, each of said conditional and said unconditional branch instructions having an area comprising a displacement to designate a jumped address, a bit width of said displacement area of said conditional branch instruction being different than a bit width of said displacement area of said unconditional branch instruction.
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Abstract
Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.
20 Citations
21 Claims
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1. A CPU capable of processing instructions in an instruction set and formed on a semiconductor chip, comprising:
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said instructions having an instruction length of each of the instructions to be processed by said CPU in said instruction set being of a first bit length; an instruction register coupled to an instruction memory storing said instructions to be processed by said CPU in said instruction set, wherein a one instruction fetched in the instruction register has a displacement value; decode means being supplied with said one instruction fetched in said instruction register and decoding said one instruction supplied from said instruction register; an execution unit performing an operation of data, wherein the maximum data word length of said data to be processed by said execution unit is a second bit length; a program counter storing an address of said one instruction fetched to said instruction register; and wherein data stored in an address which is indicated by adding the address stored in said program counter to the displacement value is provided to said execution unit when the execution unit performs an operation for immediate data having a bit length of greater than said first bit length; and
,wherein said instruction set has at least one conditional branch instruction and at least one unconditional branch instruction, each of said conditional and said unconditional branch instructions having an area comprising a displacement to designate a jumped address, a bit width of said displacement area of said conditional branch instruction being different than a bit width of said displacement area of said unconditional branch instruction. - View Dependent Claims (2, 3, 4, 5)
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6. A CPU capable of processing instructions in an instruction set and formed on a semiconductor chip, comprising:
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said instructions having an instruction length of each of the instructions to be processed by said CPU in said instruction set being of a first bit length; an instruction register coupled to an instruction memory storing said instructions to be processed by said CPU in said instruction set, wherein a one instruction fetched in the instruction register has a displacement value; decode means being supplied with said one instruction fetched in said instruction register and decoding said one instruction supplied from said instruction register; an execution unit performing an operation of data, wherein a maximum data word length of said data to be processed by said execution unit is a second bit length; and a program counter storing an address of said instruction fetched to said instruction register, wherein data stored in an address which is indicated by adding the address stored in said program counter to the displacement value is provided to said execution unit when the execution unit performs an operation for immediate data having a bit length of greater than said first bit length, wherein said first bit length is 16 bits, said second bit length is 32 bits, and wherein said instruction set has at least one conditional branch instruction and at least one unconditional branch instruction, each of said conditional and said unconditional branch instructions having an area comprising a displacement designating a jumped address, a bit width of said displacement area of said conditional branch instruction being 8 bits and said displacement area of said unconditional branch instruction being 12 bits. - View Dependent Claims (7, 8, 9)
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10. A CPU, capable of processing instructions in an instruction set comprising:
an instruction register fetching an instruction from an instruction memory storing said instructions to be processed by said CPU, wherein each instruction in said instruction set has an instruction length essentially consisting of 2n bits, where n represents a whole number; a program counter storing an address of an instruction to be fetched to said instruction register; and an execution unit performing an operation of data, each of which contains 2m bits, where m represents a whole number, wherein said instruction length is shorter than the maximum data word length of said data to be processed by said execution unit, and wherein said instruction set has at least one conditional branch instruction and at least one unconditional branch instruction, each of said conditional and said unconditional branch instructions having an area designating a displacement to a jumped address, a bit width of said displacement area of said conditional branch instruction being different from a bit width of said displacement area of said unconditional branch instruction. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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17. A CPU, capable of processing instructions in an instruction set comprising:
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an instruction register fetching an instruction from an instruction memory storing said instructions to be processed by said CPU, each instruction in said instruction set having an instruction length of a first bit length; a program counter storing an address of an instruction to be fetched to said instruction register; and an execution unit performing an operation of data, wherein a load instruction in said instruction set has a displacement, wherein data stored in an address which is indicated by adding an address in said program counter to said displacement is provided to said execution unit when the execution unit performs the load instruction for immediate data having a bit length equal to or greater than said first bit length, wherein said first bit length is shorter than the maximum data word length of said data to be processed by said execution unit, and wherein said instruction set has at least one conditional branch instruction and at least one unconditional branch instruction, each of said conditional and said unconditional branch instructions having an area designating a displacement to a jumped address, a bit width of said displacement of said conditional branch instruction being different from a bit width of said displacement of said unconditional branch instruction. - View Dependent Claims (18, 19, 20, 21)
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Specification
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Litigation Data
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Current AssigneeSOTA Semiconductor LLC (Acacia Research Corporation)
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Original AssigneeHitachi, Ltd., Hitachi Microcomputer System Limited, Hitachi Vlsi Engineering Corporation
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InventorsMasumura, Shigeki, Noguchi, Kouki, Kawasaki, Shumpei, Tawara, Yasuhiro, Watabe, Mitsuru, Sakakibara, Eiji, Kashiwagi, Yugo, Fukada, Kaoru, Fujita, Shuya, Yamazaki, Takanaga, Ishida, Katsuhiko, Akao, Yasushi, Sawa, Noriko, Baba, Shiro, Asano, Yoichi, Kihara, Toshimasa, Chaki, Hideaki, Kurakazu, Keiichi, Sugawara, Tadahiko, Tsukamoto, Takashi, Kainaga, Masahiro
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Primary Examiner(s)Bowler, Alyssa H.
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Assistant Examiner(s)FOLLANSBEE, JOHN A
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Application NumberUS08/478,730Time in Patent Office1,630 DaysField of Search395/375, 395/800, 395/800.1, 395/376, 395/820.33, 395/561US Class Current712/33CPC Class CodesG06F 2207/5352 Non-restoring division not ...G06F 7/535 Dividing onlyG06F 9/30 Arrangements for executing ...G06F 9/3001 Arithmetic instructionsG06F 9/30112 comprising data of variable...G06F 9/3013 according to data content, ...G06F 9/30145 Instruction analysis, e.g. ...G06F 9/30149 of variable length instruct...G06F 9/3016 Decoding the operand specif...G06F 9/30163 with implied specifier, e.g...G06F 9/30167 of immediate specifier, e.g...G06F 9/30181 Instruction operation exten...G06F 9/30189 according to execution mode...G06F 9/322 for non-sequential addressG06F 9/324 using program counter relat...G06F 9/3557 using program counter as ba...G06F 9/3802 Instruction prefetchingG06F 9/3814 Implementation provisions o...G06F 9/3836 Instruction issuing, e.g. d...G06F 9/3858 Result writeback, i.e. upda...View All
