Method for fabricating a semiconductor device having a tapered contact hole
DC
First Claim
1. A method for fabricating a semiconductor device comprising the steps of:
- (a) forming a field oxide layer on a semiconductor substrate;
(b) forming a transistor having an active region on said semiconductor substrate, thereby forming a resulting structure;
(c) planarizing the resulting structure by forming an interlayer insulating layer; and
(d) taper etching the interlayer insulating layer to form a tapered contact hole exposing said active region adjacent to said field oxide layer, wherein an upper portion of said tapered contact hole is wider than a lower portion thereof so that said field oxide is not etched during said taper etching process.
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Accused Products
Abstract
A semiconductor device includes: a field oxide layer formed on a semiconductor substrate; a transistor having an active region formed on a semiconductor substrate; an interlayer insulating layer formed on the transistor and the field oxide; and a tapered contact hole exposing the active region adjacent to the field oxide layer, wherein an upper portion of the tapered contact hole is wider than a lower portion thereof so that the field oxide is not etched during the contact hole etching process. A method for fabricating a semiconductor device includes the steps for: forming a field oxide layer on a semiconductor substrate; forming a transistor having an active region on a semiconductor substrate; forming an interlayer insulating layer on the resulting structure; and forming a tapered contact hole exposing the active region adjacent to the field oxide layer, wherein an upper portion of the tapered contact hole is wider than a lower portion thereof so that the field oxide is not etched during the contact hole etching process.
5 Citations
3 Claims
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1. A method for fabricating a semiconductor device comprising the steps of:
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(a) forming a field oxide layer on a semiconductor substrate; (b) forming a transistor having an active region on said semiconductor substrate, thereby forming a resulting structure; (c) planarizing the resulting structure by forming an interlayer insulating layer; and (d) taper etching the interlayer insulating layer to form a tapered contact hole exposing said active region adjacent to said field oxide layer, wherein an upper portion of said tapered contact hole is wider than a lower portion thereof so that said field oxide is not etched during said taper etching process. - View Dependent Claims (2, 3)
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Specification
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- Resources
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Current AssigneeMOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
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Original AssigneeHyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
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InventorsLee, Byung Suk, Yoon, Yong Hyeock, Jeong, Ei Sam, Kim, Sang Wook
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Primary Examiner(s)Everhart, Caridad
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Assistant Examiner(s)LEE, GRANVILL D
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Application NumberUS08/744,805Time in Patent Office1,385 DaysField of Search438/238, 438/253, 438/254, 438/255, 438/256, 438/396, 438/701, 438/723US Class Current438/254CPC Class CodesH01L 28/91 made by depositing layers, ...H10B 12/033 the capacitor extending ove...
