I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures

DC CAFC

US 6,119,181 A
Filed: 10/08/1997
Issued: 09/12/2000
Est. Priority Date: 12/20/1996
Status: Expired due to Term

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First Claim

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1. A bus system, comprising:

a processing unit, the processing unit having a multi-dimensional programmable cell architecture;

a first plurality of individual lines positioned within the processing unit, the first plurality of individual lines being bundled;

at least one interface unit coupled to the plurality of individual lines, the at least one interface unit combining the first plurality of individual lines to form the bus system, the first plurality of individual lines providing communication, via the at least one interface unit, between the processing unit and at least one of;

i) an additional processing unit, ii) a memory device, and iii) a peripheral device; and

at least one state machine for controlling the at least one interface unit.

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Abstract

A uniform bus system is provided which operates without any special consideration by a programmer. Memories and peripheral may be connected to this bus system without any special measures. Likewise, units may be cascaded with the help of the bus system. The bus system combines a number of internal lines, and leads them as a bundle to terminals. The bus system control is predefined and does not require any influence by the programmer. Any number of memories, peripherals or other units can be connected to the bus system.

231 Citations

35 Claims

1. A bus system, comprising:
- a processing unit, the processing unit having a multi-dimensional programmable cell architecture;
  
  a first plurality of individual lines positioned within the processing unit, the first plurality of individual lines being bundled;
  
  at least one interface unit coupled to the plurality of individual lines, the at least one interface unit combining the first plurality of individual lines to form the bus system, the first plurality of individual lines providing communication, via the at least one interface unit, between the processing unit and at least one of;
  
  i) an additional processing unit, ii) a memory device, and iii) a peripheral device; and
  
  at least one state machine for controlling the at least one interface unit.
- View Dependent Claims (2)
- - 2. The bus system of claim 1, wherein the at least one state machine controls an external bus.

3. A bus system, comprising:
- a processing unit, the processing unit having a multi-dimensional programmable cell architecture;
  
  a first plurality of individual lines positioned within the processing unit, the first plurality of individual lines being bundled;
  
  at least one interface unit coupled to the plurality of individual lines, the at least one interface unit combining the first plurality of individual lines to form the bus system, the first plurality of individual lines providing communication, via the at least one interface unit, between the processing unit and at least one of;
  
  i) an additional processing unit, ii) a memory device, and iii) a peripheral device; and
  
  an address generator in communication with the processing unit, the address generator generating an address for selecting a unit coupled to the bus system.

4. A bus system, comprising:
- a processing unit, the processing unit having a multi-dimensional programmable cell architecture;
  
  a first plurality of individual lines positioned within the processing unit, the first plurality of individual lines being bundled;
  
  at least one interface unit coupled to the plurality of individual lines, the at least one interface unit combining the first plurality of individual lines to form the bus system, the first plurality of individual lines providing communication, via the at least one interface unit, between the processing unit and at least one of;
  
  i) an additional processing unit, ii) a memory device, and iii) a peripheral device; and
  
  a second plurality of lines coupled to the at least one interface unit, the second plurality of lines for at least one of reading data and writing data.

5. A bus system, comprising:
- a processing unit, the processing unit having a multi-dimensional programmable cell architecture;
  
  a first plurality of individual lines positioned within the processing unit, the first plurality of individual lines being bundled;
  
  at least one interface unit coupled to the plurality of individual lines, the at least one interface unit combining the first plurality of individual lines to form the bus system, the first plurality of individual lines providing communication, via the at least one interface unit, between the processing unit and at least one of;
  
  i) an additional processing unit, ii) a memory device, and iii) a peripheral device; and
  
  at least one internal bus system coupled to the at least one interface unit, the at least one internal bus system including a plurality of individual lines, the at least one internal bus system for at least one of reading data and writing data.

6. A bus system, comprising:
- a processing unit, the processing unit having a multi-dimensional programmable cell architecture;
  
  a first plurality of individual lines positioned within the processing unit, the first plurality of individual lines being bundled;
  
  at least one interface unit coupled to the plurality of individual lines, the at least one interface unit combining the first plurality of individual lines to form the bus system, the first plurality of individual lines providing communication, via the at least one interface unit, between the processing unit and at least one of;
  
  i) an additional processing unit, ii) a memory device, and iii) a peripheral device; and
  
  at least one register coupled to the plurality of lines for managing and controlling the bus system.

7. A bus system, comprising:
- a processing unit, the processing unit having a multi-dimensional programmable cell architecture;
  
  a first plurality of individual lines positioned within the processing unit, the first plurality of individual lines being bundled;
  
  at least one interface unit coupled to the plurality of individual lines, the at least one interface unit combining the first plurality of individual lines to form the bus system, the first plurality of individual lines providing communication, via the at least one interface unit, between the processing unit and at least one of;
  
  i) an additional processing unit, ii) a memory device, and iii) a peripheral device;
  
  a bus master unit coupled to the plurality of lines for controlling the bus system; and
  
  a plurality of slave units in communication with the bus master unit.

8. A bus system, comprising:
- a processing unit, the processing unit having a multi-dimensional programmable cell architecture;
  
  a first plurality of individual lines positioned within the processing unit, the first plurality of individual lines being bundled, the first plurality of individual lines providing communication between the processing unit and at least one of;
  
  i) an additional processing unit, ii) a memory device and iii) a peripheral device;
  
  at least one interface unit coupled to the plurality of individual lines, the at least one interface unit combining the plurality of individual lines to form the bus system;
  
  a bus master unit coupled to the plurality of lines and controlling the bus system; and
  
  a plurality of slave units in communication with the bus master unit;
  
  wherein control of the bus system is transferred dynamically from the bus master unit to another unit coupled to the bus system.
- View Dependent Claims (9)
- - 9. The bus system of claim 8, wherein at least one of the plurality of slave units request control of the bus system.

10. A bus system, comprising:
- a processing unit, the processing unit having a multi-dimensional programmable cell architecture;
  
  a first plurality of individual lines positioned within the processing unit, the first plurality of individual lines being bundled;
  
  at least one interface unit coupled to the plurality of individual lines, the at least one interface unit combining the first plurality of individual lines to form the bus system, the first plurality of individual lines providing communication, via the at least one interface unit, between the processing unit and at least one of;
  
  i) an additional processing unit, ii) a memory device, and iii) a peripheral device; and
  
  a register in communication with the at least one interface unit, the register indicating whether data is stored in the at least one interface unit.

11. A bus system, comprising:
- a processing unit, the processing unit having a multi-dimensional programmable cell architecture;
  
  a first plurality of individual lines positioned within the processing unit, the first plurality of individual lines being bundled, the first plurality of individual lines providing communication between the processing unit and at least one of;
  
  i) an additional processing unit, ii) a memory device and iii) a peripheral device; and
  
  at least one interface unit coupled to the plurality of individual lines, the at least one interface unit combining the first plurality of individual lines to form the bus system, the at least one interface unit being at least one of integral with the processing unit and formed by a configuration of a plurality of logic cells, each of the plurality of logic cells implementing simple logical functions according to a logic cell configuration.

12. A bus system, comprising:
- a processing unit, the processing unit having a multi-dimensional programmable cell architecture;
  
  a first plurality of individual lines positioned within the processing unit, the first plurality of individual lines being bundled, the first plurality of individual lines providing communication between the processing unit and at least one of;
  
  i) an additional processing unit, ii) a memory device and iii) a peripheral device; and
  
  at least one interface unit coupled to the plurality of individual lines, the at least one interface unit combining the first plurality of individual lines to form the bus system, the at least one interface unit being configured by at least one of a primary logic unit and the processing unit.
- View Dependent Claims (13)
- - 13. The bus system of claim 12, wherein the primary logic unit is at least partially integrated with the processing unit.

14. A bus system, comprising:
- a processing unit, the processing unit having a multi-dimensional programmable cell architecture;
  
  a first plurality of individual lines positioned within the processing unit, the first plurality of individual lines being bundled;
  
  at least one interface unit coupled to the plurality of individual lines, the at least one interface unit combining the first plurality of individual lines to form the bus system, the first plurality of individual lines providing communication, via the at least one interface unit, between the processing unit and at least one of;
  
  i) an additional processing unit, ii) a memory device, and iii) a peripheral device; and
  
  at least one connection to at least one of a data flow processor (DFP), a field programmable gate array (FPGA), and a dynamically programmable gate array (DPGA).

15. A bus system, comprising:
- a processing unit, the processing unit having a multi-dimensional programmable cell architecture, the processing unit including a plurality of re-programmable, dynamically reconfigurable cells; and
  
  a plurality of individual lines positioned within the processing unit, the plurality of individual lines being bundled;
  
  wherein the plurality of individual lines provide communication between the processing unit and at least one of;
  
  i) an additional processing unit, ii) a memory device, and iii) a peripheral device.
- View Dependent Claims (16)
- - 16. The bus system according to claim 15, wherein the memory device is external to the processing unit.

17. A bus system, comprising:
- a processing unit, the processing unit having a multi-dimensional programmable cell architecture, the processing unit including a plurality of re-programmable, dynamically reconfigurable cells;
  
  a first plurality of individual lines positioned within the processing unit, the first plurality of individual lines being bundled; and
  
  at least one interface unit coupled to the plurality of individual lines, the at least one interface unit combining the first plurality of individual lines to form the bus system, the first plurality of individual lines providing communication, via the at least one interface unit, between the processing unit and at least one of;
  
  i) an additional processing unit, ii) a memory device, and iii) a peripheral device.
- View Dependent Claims (18)
- - 18. The bus system according to claim 17, wherein the memory device is external to the processing unit.

19. A bus system, comprising:
- a processing unit, the processing unit having a multi-dimensional programmable cell architecture;
  
  a bus positioned within the processing unit;
  
  at least one interface unit coupled to the bus, the bus providing communication, via the at least one interface unit, between the processing unit and at least one of;
  
  i) an additional processing unit, ii) a memory device, and iii) a peripheral device; and
  
  at least one state machine for controlling the at least one interface unit.
- View Dependent Claims (20)
- - 20. The bus system of claim 19, wherein the at least one state machine controls an external bus.

21. A bus system, comprising:
- a processing unit, the processing unit having a multi-dimensional programmable cell architecture;
  
  a bus positioned within the processing unit;
  
  at least one interface unit coupled to the bus, the bus providing communication, via the at least one interface unit, between the processing unit and at least one of;
  
  i) an additional processing unit, ii) a memory device, and iii) a peripheral device; and
  
  an address generator in communication with the processing unit, the address generator generating an address for selecting a unit coupled to the bus.

22. A bus system, comprising:
- a processing unit, the processing unit having a multi-dimensional programmable cell architecture;
  
  a first bus positioned within the processing unit;
  
  at least one interface unit coupled to the first bus, the first bus providing communication, via the at least one interface unit, between the processing unit and at least one of;
  
  i) an additional processing unit, ii) a memory device, and iii) a peripheral device; and
  
  a second bus coupled to the at least one interface unit, the second bus for at least one of reading data and writing data.

23. A bus system, comprising:
- a processing unit, the processing unit having a multi-dimensional programmable cell architecture;
  
  a first bus positioned within the processing unit;
  
  at least one interface unit coupled to the first bus, the first bus providing communication, via the at least one interface unit, between the processing unit and at least one of;
  
  i) an additional processing unit, ii) a memory device, and iii) a peripheral device; and
  
  at least one internal bus system coupled to the at least one interface unit, the at least one internal bus system for at least one of reading data and writing data.

24. A bus system, comprising:
- a processing unit, the processing unit having a multi-dimensional programmable cell architecture;
  
  a first bus positioned within the processing unit;
  
  at least one interface unit coupled to the bus, the first bus providing communication, via the at least one interface unit, between the processing unit and at least one of;
  
  i) an additional processing unit, ii) a memory device, and iii) a peripheral device; and
  
  at least one register coupled to the first bus for managing and controlling the bus system.

25. A bus system, comprising:
- a processing unit, the processing unit having a multi-dimensional programmable cell architecture;
  
  a first bus positioned within the processing unit;
  
  at least one interface unit coupled to the first bus, the first bus providing communication, via the at least one interface unit, between the processing unit and at least one of;
  
  i) an additional processing unit, ii) a memory device, and iii) a peripheral device; and
  
  a bus master unit coupled to the first bus for controlling the bus system; and
  
  a plurality of slave units in communication with the bus master unit.

26. A bus system, comprising:
- a processing unit, the processing unit having a multi-dimensional programmable cell architecture;
  
  a first bus positioned within the processing unit, the first bus providing communication between the processing unit and at least one of;
  
  i) an additional processing unit, ii) a memory device and iii) a peripheral device;
  
  at least one interface unit coupled to the first bus;
  
  a bus master unit coupled to the first bus and controlling the bus system; and
  
  a plurality of slave units in communication with the bus master unit;
  
  wherein control of the bus system is transferred dynamically from the bus master unit to another unit coupled to the bus system.
- View Dependent Claims (27)
- - 27. The bus system of claim 26, wherein at least one of the plurality of slave units request control of the bus system.

28. A bus system, comprising:
- a processing unit, the processing unit having a multi-dimensional programmable cell architecture;
  
  a first bus positioned within the processing unit, the first plurality of individual lines being bundled;
  
  at least one interface unit coupled to the first bus, first bus providing communication, via the at least one interface unit, between the processing unit and at least one of;
  
  i) an additional processing unit, ii) a memory device, and iii) a peripheral device; and
  
  a register in communication with the at least one interface unit, the register indicating whether data is stored in the at least one interface unit.

29. A bus system, comprising:
- a processing unit, the processing unit having a multi-dimensional programmable cell architecture;
  
  a first bus positioned within the processing unit, the first bus providing communication between the processing unit and at least one of;
  
  i) an additional processing unit, ii) a memory device and iii) a peripheral device; and
  
  at least one interface unit coupled to the first bus, the at least one interface unit being at least one of integral with the processing unit and formed by a configuration of a plurality of logic cells, each of the plurality of logic cells implementing simple logical functions according to a logic cell configuration.

30. A bus system, comprising:
- a processing unit, the processing unit having a multi-dimensional programmable cell architecture;
  
  a first bus positioned within the processing unit, the first bus providing communication between the processing unit and at least one of;
  
  i) an additional processing unit, ii) a memory device and iii) a peripheral device; and
  
  at least one interface unit coupled to the first bus, the at least one interface unit being configured by at least one of a primary logic unit and the processing unit.
- View Dependent Claims (31)
- - 31. The bus system of claim 30, wherein the primary logic unit is at least partially integrated with the processing unit.

32. A bus system, comprising:
- a processing unit, the processing unit having a multi-dimensional programmable cell architecture;
  
  a first bus positioned within the processing unit;
  
  at least one interface unit coupled to the first bus, the first bus providing communication, via the at least one interface unit, between the processing unit and at least one of;
  
  i) an additional processing unit, ii) a memory device, and iii) a peripheral device; and
  
  at least one connection to at least one of a data flow processor (DFP), a field programmable gate array (FPGA), and a dynamically programmable gate array (DPGA).

33. A bus system, comprising:
- a processing unit, the processing unit having a multi-dimensional programmable cell architecture, the processing unit including a plurality of re-programmable, dynamically reconfigurable cells; and
  
  a bus positioned within the processing unit;
  
  wherein the bus provides communication between the processing unit and at least one of;
  
  i) an additional processing unit, ii) a memory device, and iii) a peripheral device.
- View Dependent Claims (34)
- - 34. The bus system according to claim 33, wherein the memory device is external to the processing unit.

35. A bus system, comprising:
- a processing unit, the processing unit having a multi-dimensional programmable cell architecture, the processing unit including a plurality of re-programmable, dynamically reconfigurable cells;
  
  a first bus positioned within the processing unit; and
  
  at least one interface unit coupled to the first bus, the first bus providing communication, via the at least one interface unit, between the processing unit and at least one of;
  
  i) an additional processing unit, ii) a memory device, and iii) a peripheral device.

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Current Assignee
Scientia Sol Mentis AG (PACT XPP Schweiz AG)
Original Assignee
Pact GmbH
Inventors
Vorbach, Martin, Munch, Robert
Primary Examiner(s)
Ray, Gopal C.

Application Number

US08/947,254
Time in Patent Office

1,070 Days
Field of Search

395/280, 395/309, 395/800.11, 395/80.25, 395/800.29, 395/377, 326/38, 326/39, 326/41, 364/489, 370/419, 710/100, 710/129, 710/110, 712/11, 712/14, 712/18, 712/25, 712/29, 712/31, 711/100
US Class Current

710/100
CPC Class Codes

G06F 15/7867 with reconfigurable archite...

G11C 7/10 Input/output [I/O] data int...

I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures

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I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures

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4 Assignments

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Reexamination

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Abstract

231 Citations

35 Claims

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