Semiconductor circuit design method for employing spacing constraints and circuits thereof
DCFirst Claim
1. A semiconductor circuit design method comprising:
- defining a spacing constraint which describes a desired spacing between a transistor gate line and a next adjacent structure;
providing a circuit layout defining a plurality of transistor gate lines;
determining from said circuit layout at least one area wherein said spacing constraint is not met; and
modifying said circuit layout by defining in said one area at least one added space-compensating structure which is laterally spaced from a gate line and a next adjacent structure where said spacing constraint is not met.
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Abstract
Semiconductor circuit design methods, semiconductor processing methods, and related integrated circuitry are described. In one embodiment, a spacing constraint is defined and describes a desired spacing between a transistor gate line and a next adjacent structure. A circuit layout is defined to include a plurality of transistor gate lines. From the circuit layout, at least one area is determined wherein the spacing constraint is not met. The circuit layout is modified by defining in the one determined area, at least one added space-compensating structure which is laterally spaced from a gate line and a next adjacent structure where the spacing constraint is not met. In another embodiment, a plurality of gate lines are defined which are to be formed over substrate active areas. A determination is made whether a gate line spacing constraint is met wherein the gate line spacing constraint describes a desired spacing between a transistor gate line and a next adjacent transistor gate line. If the spacing constraint is not met, then a space-compensating transistor gate line is added and positioned to satisfy the spacing constraint.
28 Citations
46 Claims
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1. A semiconductor circuit design method comprising:
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defining a spacing constraint which describes a desired spacing between a transistor gate line and a next adjacent structure;
providing a circuit layout defining a plurality of transistor gate lines;
determining from said circuit layout at least one area wherein said spacing constraint is not met; and
modifying said circuit layout by defining in said one area at least one added space-compensating structure which is laterally spaced from a gate line and a next adjacent structure where said spacing constraint is not met. - View Dependent Claims (2, 3, 4, 5)
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6. A semiconductor circuit design method comprising:
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defining a plurality of transistor gate lines which are to be formed over substrate active areas;
determining whether a gate line spacing constraint is met, said spacing constraint describing a desired spacing between a transistor gate line and a next adjacent transistor gate line; and
if said spacing constraint is not met, adding a space-compensating transistor gate line positioned to satisfy said spacing constraint. - View Dependent Claims (7, 8, 9, 10, 11)
the defining of the transistor gate lines comprises;
defining isolated gate lines which have no lateral neighboring transistor gate line within about 5 units;
defining edge gate lines which have no neighboring lateral gate lines on one side within about 5 units; and
defining center gate lines which have lateral neighboring gate lines on each side within about 5 units, where “
units”
is defined as an integer number, which, when multiplied by a selected scaling factor value, yields a product which represents the actual spacing value; and
the adding of the space-compensating transistor gate line comprises forming at least one space-compensating transistor gate line to effectively redefine at least one of the isolated gate lines and at least one of the edge gate lines as center gate lines.
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11. The semiconductor circuit design method of claim 6, wherein:
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the defining of the transistor gate lines comprises;
defining isolated gate lines which have no lateral neighboring transistor gate line within about 1.2 microns;
defining edge gate lines which have no neighboring lateral gate lines on one side within about 1.2 microns; and
defining center gate lines which have lateral neighboring gate lines on each side within about 1.2 microns; and
the adding of the space-compensating transistor gate line comprises forming at least one space-compensating transistor gate line to effectively redefine at least one of the isolated gate lines and at least one of the edge gate lines as center gate lines.
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12. A semiconductor circuit design method comprising:
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examining a circuit layout having a memory area defining memory circuitry which is to be formed, and a peripheral area defining peripheral circuitry which is to be formed;
ascertaining from the circuit layout areas in which retrofit structure patterns are to be added; and
retrofitting the circuit layout within the peripheral area with retrofit structure patterns which ensure that desired spacing constraints are met with respect to at least one gate line structure within the peripheral area when said peripheral circuitry formed in the peripheral area is subsequently patterned and etched. - View Dependent Claims (13, 14, 15, 16, 17, 18)
the peripheral circuitry comprises conductive lines; and
the retrofitting of the circuit layout comprises adding retrofit structure patterns in the form of additional conductive lines at least some of which having widths which are different from one another.
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17. The semiconductor circuit design method of claim 12, wherein:
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the peripheral circuitry comprises conductive lines having generally uniform conductive line widths; and
the retrofitting of the circuit layout comprises adding retrofit structure patterns in the form of additional conductive lines at least some of which having widths which are different from the uniform conductive line widths.
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18. The semiconductor circuit design method of claim 12, wherein:
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the peripheral circuitry comprises conductive lines; and
the retrofitting of the circuit layout comprises adding retrofit structure patterns in the form of additional conductive lines at least some of which having widths which are different from one another and being in electrical communication with one peripheral circuitry conductive line.
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19. A semiconductor processing method comprising:
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forming a masking layer over a substrate, the masking layer defining a plurality of conductive lines which are to be etched, some of the defined conductive lines constituting active gate lines positioned over substrate active areas, other of the defined conductive lines constituting space-compensating conductive lines at least some of which having portions positioned over isolation oxide areas and being defined by the masking layer only to satisfy a spacing constraint which describes a desired active gate line-to-gate line spacing; and
etching to form the plurality of conductive lines through the masking layer. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26)
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- 27. A semiconductor processing method comprising forming a plurality of conductive lines over a substrate, some of the conductive lines providing transistor gate lines over substrate active areas, other of the conductive lines being formed only to satisfy a spacing constraint which describes a desired spacing between the transistor gate lines.
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37. Integrated circuitry comprising:
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a semiconductive substrate comprising active areas;
a plurality of conductive lines disposed over the semiconductive substrate, some of the conductive lines providing transistor gate lines over said active areas, other of the conductive lines being disposed only to satisfy a spacing constraint which describes a desired spacing between the transistor gate lines. - View Dependent Claims (38, 39, 40, 41, 42)
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43. A semiconductor processing method comprising:
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forming a plurality of conductive lines over substrate active areas, said plurality of conductive lines comprising (a) edge lines, (b) isolated lines, and (c) center lines; and
for the edge lines and isolated lines, forming additional space-compensating structures proximate at least some of the edge and isolated lines and spaced-apart from a side or sides, respectively, which have no immediate conductive line neighbor within a selected distance, and wherein the additional space-compensating structures meet a spacing constraint by having portions which are formed no further away from their associated edge or isolated line than the selected distance.
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44. A semiconductor processing method comprising:
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forming a plurality of conductive lines over substrate active areas, said plurality of conductive lines comprising (a) edge lines which have no immediate conductive line neighbor on only one side thereof from between about four to six units away, (b) isolated lines which have no immediate conductive line neighbor on either side thereof from between about four to six units away, and (c) center lines which have immediate conductive line neighbors on each side thereof from between about four to six units away, where “
units”
is defined as an integer number, which, when multiplied by a selected scaling factor value, yields a product which represents the actual spacing value, the center lines having generally uniform associated channel lengths; and
for the edge lines and isolated lines, forming additional space-compensating structures meeting a spacing constraint, the additional structures proximate at least some of the edge and isolated lines and spaced-apart from the side or sides, respectively, which have no immediate conductive line neighbor within about four to six units away, and wherein the additional space-compensating structures have portions which are formed no further than between about four to six units away from their associated edge or isolated line, the edge lines and isolated lines having respective associated channel lengths which are substantially the same as the channel lengths of the center lines. - View Dependent Claims (45)
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46. A semiconductor processing method comprising manufacturing a plurality of integrated circuitry devices comprising transistor gate lines in accordance with a design rule, said design rule comprising providing for the addition of space-compensating structures to at least one of the integrated circuitry devices, such structures added within a predetermined distance laterally proximate at least one transistor gate line.
Specification