Method for forming multi-layer interconnection of a semiconductor device

Disclosed is a method for forming multi-layer interconnection of semiconductor device, which allows a contact hole to be formed at a size smaller than a resolution limit of the exposing system. The method comprises the steps of: providing a semiconductor substrate on which a first interconnection layer is formed; forming a first interlayer insulating film on the first interconnection layer and the semiconductor substrate; forming a patterned etch stopper layer on the first interlayer insulating film such that the etch stopper layer is overlapped with a portion of the first interconnection layer; forming a second interlayer insulating film on the etch stopper layer and the first interlayer insulating film; forming a photoresist pattern on the second interlayer insulating film in such a manner that a portion of the second interlayer insulating film, which is vertically overlapped with a portion of the first interconnection layer and a portion of the etch stopper layer including the portion overlapped with the first interconnection layer, is exposed; etching the second and first interlayer films using the photoresist pattern and the etch stopper layer such that a contact hole is formed through which the first interconnection layer and a portion of the etch stopper layer are exposed; removing the photoresist pattern; depositing a conductive film at a uniform thickness on the second interlayer insulating film, side walls of the contact hole, the first interconnection layer, and the etch stopper layer; and patterning the conductive film such that a second interconnection layer is formed that is in contact with the first interconnection layer.