I/O and memory bus system for DFPS and units with two or multi-dimensional programmable cell architectures
DC CAFC
First Claim
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1. A bus system, comprising:
- a plurality of at least one of individual lines, buses, and subbuses within at least one of a unit including at least one of a data flow processor (DFP), a field programmable gate array (FPGA), a dynamically programmable gate array (DPGA), and a unit having a multi-dimensional programmable cell architecture, the plurality of the at least one of individual lines, buses and subbuses being bundled, wherein the plurality of the at least one individual lines, buses and subbuses at least one of combines multiple units and connects at least one of memories and peripherals.
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Abstract
A general bus system is provided which combines a number of internal lines and leads them as a bundle to the terminals. The bus system control is predefined and does not require any influence by the programmer. Any number of memories, peripherals or other units can be connected to the bus system (for cascading).
288 Citations
18 Claims
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1. A bus system, comprising:
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a plurality of at least one of individual lines, buses, and subbuses within at least one of a unit including at least one of a data flow processor (DFP), a field programmable gate array (FPGA), a dynamically programmable gate array (DPGA), and a unit having a multi-dimensional programmable cell architecture, the plurality of the at least one of individual lines, buses and subbuses being bundled, wherein the plurality of the at least one individual lines, buses and subbuses at least one of combines multiple units and connects at least one of memories and peripherals. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
a register indicating whether data is stored in the at least one interface.
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9. The bus system according to claim 1, further comprising:
an address generator generating addresses for the units to be contacted via the bus system.
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10. The bus system according to claim 1, further comprising:
a register for managing and controlling the bus system.
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11. The bus system according to claim 1, wherein the bus is controlled by a unit which accesses a plurality of lower-level units.
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12. The bus system according to claim 11, wherein a lower-level unit requests a bus control.
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13. The bus system according to claim 1, wherein standard bus systems are used.
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14. The bus system according to claim 1, wherein the unit includes additional ordinary connections in a manner customary with at least one of the DFP, the FPGA and the DPGA.
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15. A bus system, comprising:
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a plurality of at least one of individual lines, buses, and subbuses within at least one of a unit including at least one of a data flow processor (DFP), a field programmable gate array (FPGA), a dynamically programmable gate array (DPGA), and a unit having a multi-dimensional programmable cell architecture by means of which multiple units can be combined and/or memories and/or peripherals can be connected, the plurality of the at least one of individual lines, buses and subbuses being bundled, wherein the plurality of the at least one individual lines, buses and subbuses at least one of combines multiple units and connects at least one of memories and peripherals, and wherein a bus control is transferred dynamically from one unit to another.
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16. A bus system, comprising:
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a plurality of at least one of individual lines, buses and subbuses within at least one of a unit including at least one of a data flow processor (DFP), a field programmable gate array (FPGA) a dynamically programmable gate array (DPGA), and a unit having a multi-dimensional programmable cell architecture, the plurality of the at least one of individual lines, buses and subbuses being bundled, wherein the plurality of the at least one individual lines, buses and subbuses at least one of combines multiple units and connects at least one of memories and peripherals, wherein at least one interface combines the lines and creates the bus system, and wherein the at least one interface is at least one of implemented directly on the unit and is created via a configuration of logic cells. - View Dependent Claims (17)
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18. A bus system, comprising:
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a plurality of at least one of individual lines, buses, and subbuses within at least one of a unit including at least one of a data flow processor (DFP), a field programmable gate array (FPGA), a dynamically programmable gate array (DPGA), and a unit having a multi-dimensional programmable cell architecture, the plurality of the at least one of individual lines, buses and subbuses being bundled, wherein the plurality of the at least one individual lines, buses and subbuses at least one of combines multiple units and connects at least one of memories and peripherals, wherein at least one interface combines the lines and creates the bus system, and wherein the at least one interface is configured by at least one of a primary logic unit and the unit itself.
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Specification
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Litigation Data
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Current AssigneeScientia Sol Mentis AG (PACT XPP Schweiz AG)
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Original AssigneePact GmbH
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InventorsVorbach, Martin, Münch, Robert
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Primary Examiner(s)Ray, Gopal C.
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Application NumberUS09/335,974Time in Patent Office935 DaysField of Search710/100, 710/101, 710/8, 710/72, 710/126, 712/11, 712/14, 712/18, 716/17, 716/16, 326/38, 326/39, 326/41US Class Current710/100CPC Class CodesG06F 15/7867 with reconfigurable archite...G11C 7/10 Input/output [I/O] data int...H03K 19/17736 Structural details of routi...H03K 19/17744 for input/output signalsH03K 19/17796 for physical disposition of...
