Method and circuitry for bank tracking in write command sequence
DC
First Claim
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1. A memory device comprising:
- an array of memory cells arranged in a plurality of addressable blocks; and
control circuitry to access a first one of the plurality of addressable blocks in response to an externally provided command sequence and prohibits the access operation if an externally provided bank address changes during the externally provided command sequence.
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Abstract
A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The synchronous flash memory device includes an array of non-volatile memory cells arranged in a plurality of addressable blocks. Control circuitry is provided to access the plurality of addressable blocks to perform a write or erase operation on memory cells contained in a first one of the plurality of addressable blocks. The control circuitry performs the write or erase operation in response to an externally provided command sequence and prohibits the write or erase operation if an externally provided bank address changes during the externally provided command sequence.
33 Citations
15 Claims
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1. A memory device comprising:
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an array of memory cells arranged in a plurality of addressable blocks; and
control circuitry to access a first one of the plurality of addressable blocks in response to an externally provided command sequence and prohibits the access operation if an externally provided bank address changes during the externally provided command sequence. - View Dependent Claims (2, 3, 4)
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5. A memory device comprising:
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an array of memory cells arranged in a plurality of addressable blocks; and
control circuitry to access a first one of the plurality of addressable blocks in response to an externally provided command sequence, wherein the command sequence comprises a plurality of commands and one or more no-operation commands (NOP), the control circuitry prohibits the access operation if an externally provided bank address changes during the externally provided command sequence.
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6. A processing system comprising:
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a processor; and
a memory coupled to communicate with the processor, the memory device comprises, an array of memory cells arranged in a plurality of addressable blocks, and control circuitry to access a first one of the plurality of addressable blocks in response to a command sequence provided by the processor, the control circuitry prohibits the access operation if a bank address provided by the processor changes during the externally provided command sequence.
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7. A processing system comprising:
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a processor; and
a memory coupled to communicate with the processor, the memory device comprises, an array of memory cells arranged in a plurality of addressable blocks, and control circuitry to access a first one of the plurality of addressable blocks in response to a command sequence provided by the processor, wherein the command sequence comprises a plurality of commands and one or more no-operation commands (NOP), the control circuitry prohibits the access operation if a bank address provided by the processor changes during the externally provided command sequence.
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8. A method of operating a memory device, the method comprising:
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receiving an erase command sequence;
receiving a memory array bank address with the command sequence;
monitoring the bank address; and
prohibiting an erase operation if the monitored bank address changes during the erase command sequence. - View Dependent Claims (9, 10)
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11. A method of operating a memory device, the method comprising:
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receiving a write command sequence;
receiving a memory array bank address with the command sequence;
monitoring the bank address; and
prohibiting a write operation if the monitored bank address changes during the erase command sequence. - View Dependent Claims (12, 13)
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14. A method of operating a flash memory device, the method comprising:
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receiving a command sequence to initiate an array access operation;
receiving a memory array address with the command sequence;
monitoring the memory array address; and
prohibiting the array access operation if the monitored address changes during the command sequence. - View Dependent Claims (15)
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Specification
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Litigation Data
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Current AssigneeRound Rock Research LLC
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Original AssigneeMicron Technology, Inc.
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InventorsRoohparvar, Frankie F.
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Primary Examiner(s)Lam, David
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Application NumberUS09/957,833Publication NumberTime in Patent Office375 DaysField of Search365/185.11, 365/185.29, 365/185.33, 365/233, 365/185.02, 365/189.01, 365/230.03US Class Current365/185.11CPC Class CodesG11C 16/08 Address circuits; Decoders;...G11C 7/1072 for memories with random ac...G11C 7/22 Read-write [R-W] timing or ...G11C 8/12 Group selection circuits, e...
