System and method for sending and receiving data signals over a clock signal line
DC CAFC
First Claim
1. An apparatus for transmitting a clock signal and data signals over a signal line, the apparatus comprising a clock generator having a first input, a second input and an output, the clock generator modulating a falling edge of an output signal to indicate different data values, the first input of the clock generator coupled to receive a clock signal, and the second input of the clock generator coupled to receive a control signal indicating a data value to be transmitted.
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Litigations
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Accused Products
Abstract
The system preferably includes a unique transmitter that sends both clock and data signals over the same transmission line. The receiver uses the same transmission line to send data signals back to the transmitter. The transmitter comprises a clock generator, a decoder and a line interface. The clock generator produces a clock signal that includes a variable position falling edge. The falling edge position is decoded by the receiver to extract data from the clock signal. The receiver comprises a clock re-generator, a data decoder and a return channel encoder. The clock re-generator monitors the transmission line, receives signals, filters them and generates a clock signal at the receiver from the signal on the transmission line. The return channel encoder generates signals and asserts them on the transmission line. The signal is asserted or superimposed over the clock & data signal provided by the transmitter.
106 Citations
26 Claims
- 1. An apparatus for transmitting a clock signal and data signals over a signal line, the apparatus comprising a clock generator having a first input, a second input and an output, the clock generator modulating a falling edge of an output signal to indicate different data values, the first input of the clock generator coupled to receive a clock signal, and the second input of the clock generator coupled to receive a control signal indicating a data value to be transmitted.
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19. A receiver for coupling to a transmitter through a signal line, wherein the receiver comprises:
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a clock re-generator for recovering a clock signal from the signal line, the clock re-generator having an input and an output, the input of the clock re-generator coupled to the signal line; and
a data decoder for extracting data signals from the clock signal, the decoder having a first input, a second input, and an output, the first input of the decoder coupled to the signal line, the second input of the second decoder coupled to the output of the clock re-generator and the output providing data from the signal line, the data decoder comprising;
a delay-locked loop having an input and a plurality of outputs for outputting signals shifted in phase from an input signal, the input of the delay-locked loop coupled to the output of the clock re-generator; and
a flip-flop having a control input, a data input, and an output, the control input of the flip-flop coupled to one of the plurality of outputs of the delay-locked loop, the data input of the flip-flop coupled to the signal line, and the output providing data from the signal line. - View Dependent Claims (20, 21, 22, 23, 24)
a rising edge detector having an input and an output, the input coupled to the output of the delay compensator;
a delay circuit having an input and an output, the input coupled to the output of the rising edge detector; and
a latch having a control input, a data input and a data output, the control input coupled to the output of the delay circuit, the data input adapted to receive data, and the data output coupled to the input of the line interface.
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24. The receiver of claim 22, wherein the return channel encoder further comprises:
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a delay-locked loop having an input and a plurality of outputs for outputting signals shifted in phase from an input signal, the input of the delay-locked loop coupled to the output of the delay compensator; and
a flip-flop having a control input, a data input and an output, the control input of the flip-flop coupled to one of the plurality of outputs of the delay-locked loop, and the data input of the flip-flop coupled to the signal line.
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25. A method for receiving and transmitting signals using a receiver coupled to a signal line, the method comprising:
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receiving a signal on an input of a clock re-generator, the clock re-generator having an input and an output, the clock re-generator being adapted for recovering a clock signal from the signal line;
receiving a signal on a data input of a data decoder, the data decoder having a control input, a data input, and a data output, the data decoder adapted for extracting data from the signal on the data input;
passing the clock signal from the output of the clock re-generator to the control input of the data decoder;
passing the clock signal from the output of the clock re-generator to the input of a delay compensator, the delay compensator having an input and an output, the delay compensator adapted for adjusting a clock signal from a clock re-generator to compensate for propagation delay; and
transmitting data from a data output of a return channel encoder over the signal line, the return channel encoder having a control input, a data input, and a data output, the control input coupled to receive the output from the delay compensator and the data input being adapted to receive data. - View Dependent Claims (26)
receiving a signal on an input of a line interface, the line interface having an input coupled to the signal line and an output.
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Specification
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- Resources
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Current AssigneeSuper Interconnect Technologies LLC (Acacia Research Corporation)
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Original AssigneeSilicon Image, Inc. (Lattice Semiconductor Corporation)
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InventorsKim, Gyudong, Kim, Min-Kyu, Hwang, Seung Ho
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Primary Examiner(s)Pham, Chi
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Assistant Examiner(s)TRAN, KHANH C
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Application NumberUS09/393,235Time in Patent Office1,125 DaysField of Search375/219, 375/220, 375/244, 375/257, 375/288, 375/293, 375/354, 375/355, 375/359, 375/360, 375/377, 370/284, 370/301, 370/307US Class Current375/219CPC Class CodesG09G 2370/04 Exchange of auxiliary data,...G09G 5/006 Details of the interface to...G09G 5/008 Clock recoveryH04L 25/4902 Pulse width modulation; Pul...H04L 7/0008 Synchronisation information...
