Method for synchronizing pixel deposition frequencies between a plurality of print engines
DC CAFC
First Claim
Patent Images
1. A method for synchronizing a plurality of pixel generation mechanisms on a corresponding plurality of print engines comprising the steps of:
- providing a plurality of print engines, each of the print engines including a pixel deposition mechanism, the pixel deposition mechanism having a pixel deposition clock signal for providing a pixel deposition frequency for the pixel deposition mechanism;
embedding a first clock signal in data so as to produce a combined data and clock signal;
communicating the combined data and clock signal to each of the print engines;
deriving the first clock signal from the combined data and clock signal by each of the print engines; and
generating the pixel deposition clock signal for each of the plurality of pixel deposition mechanisms by each of the print engines;
whereby the pixel deposition frequency of each of the plurality of pixel deposition mechanism are generated from the first clock signal.
6 Assignments
Litigations
0 Petitions
Accused Products
Abstract
The present invention provides a system and method for simultaneously controlling a plurality of print engines connected together (in series, in parallel or otherwise) that facilitates electronic stitching between the print engines. More specifically, the present invention provides a system and method for synchronizing the pixel deposition frequencies and the drive mechanisms between the various inter-connected print engines so as to eliminate synchronization between the print engines. The method for synchronizing the pixel deposition frequencies and/or drive mechanisms between a plurality of print engines comprises the steps of: (a) coupling the plurality of print engines together with a printer controller, (b) embedding a first clock signal in data; (c) transmitting the data to the print engines; (d) each of the print engines receiving the data; (e) each of the print engines deriving a second clock signal from the data received, which is directly proportional to the first clock signal; and (f) each of the print engines driving its corresponding pixel deposition mechanism and/or its drive mechanisms with the second clock signal.
23 Citations
23 Claims
-
1. A method for synchronizing a plurality of pixel generation mechanisms on a corresponding plurality of print engines comprising the steps of:
-
providing a plurality of print engines, each of the print engines including a pixel deposition mechanism, the pixel deposition mechanism having a pixel deposition clock signal for providing a pixel deposition frequency for the pixel deposition mechanism;
embedding a first clock signal in data so as to produce a combined data and clock signal;
communicating the combined data and clock signal to each of the print engines;
deriving the first clock signal from the combined data and clock signal by each of the print engines; and
generating the pixel deposition clock signal for each of the plurality of pixel deposition mechanisms by each of the print engines;
whereby the pixel deposition frequency of each of the plurality of pixel deposition mechanism are generated from the first clock signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
transmitting the combined data and clock signal to a first one of the print engines in the print engine daisy chain; and
receiving and retransmitting the combined data and clock signal to a next one of the print engines in the print engine daisy-chain by the print engines until the combined data and clock signal is retransmitted to a last one of the print engines in the print engine daisy chain.
-
-
3. The method of claim 2, wherein the pixel deposition clock signal includes a phase and a frequency, and the method further comprises the step of:
adjusting the phase of the pixel deposition clock signal, by the print engines, according to an amount of time for the combined data and clock signal to be received by the print engines.
-
4. The method of claim 2, wherein a printer controller is coupled to a first one of the print engines in the print engine daisy-chain and the printer controller performs the embedding and transmitting steps.
-
5. The method of claim 4, wherein the printer controller is coupled to the last one of the print engines in the print engine daisy chain, and the communicating step includes the step of retransmitting the combined data and clock signal from the last print engine in the print engine daisy chain to the printer controller.
-
6. The method of claim 5, wherein:
-
the plurality of print engines are coupled together with fiber optic links;
the printer controller is coupled to the first print engine on the print engine daisy-chain with a fiber optic link;
the printer controller is coupled to the last print engine on the print engine daisy-chain with a fiber optic link;
the transmitting and retransmitting steps are performed over the fiber optic links;
the combined data and clock signal is transmitted in the transmitting step using a self-clocking data transmission code; and
the combined data and clock signal is transmitted in all of the retransmitting steps using the self-clocking data transmission code.
-
-
7. The method of claim 1, wherein the generating step includes the steps of:
-
clocking a free running counter with the first clock signal, the counter having a count output;
translating the count output to a voltage amplitude level corresponding to a respective point along a voltage wave signal period; and
converting the voltage amplitude level value to an analog voltage, the analog voltage being the pixel deposition clock signal.
-
-
8. The method of claim 7, further comprising the step of initializing the counters with a preload value, the preload value being defined according to an amount of time for the combined data and clock signal to be communicated to the print engines.
-
9. The method of claim 1, wherein the plurality of print engines are coupled to a printer controller in a star configuration, where the printer controller is at a hub of the star configuration and is coupled to each of the print engines with individual data links, and wherein the communicating step is performed over the individual data links.
-
10. A system for dispatching bitmap data to a plurality of print engines and for controlling the plurality of print engines, comprising:
-
a plurality of print engines;
a controller including a processing circuit for generating bitmap data, an output port, and an input port;
a plurality of print engine communication circuits, each of the print engine communication circuits being operatively coupled to a corresponding one of the plurality of print engines, each of the communication circuits including an input port, an output port, a bitmap data transfer circuit, and a pixel deposition clock generation circuit for generating a pixel deposition clock signal; and
a plurality of data links coupling together the controller and the plurality of print engine communication circuits in a daisy-chain configuration;
each of the bitmap data transfer circuits being coupled to the corresponding one of the plurality of print engines to provide bitmap data to the corresponding one of the plurality of print engines, and each of the pixel deposition clock generation circuits being coupled to the corresponding one of the plurality of print engines to provide a pixel deposition clock signal for the corresponding one of the plurality of print engines;
wherein the controller includes an encoder circuit, coupled to the output port of the controller, for encoding raw digital data and a first clock source into a data transmission code to be transmitted by the output port of the controller;
wherein each of the print engine communication circuits include a decoder circuit for decoding the data transmission code back into the raw digital data and into the first clock source, the decoder circuit having a data input coupled to the input port of the print engine communication circuit, a clock output coupled to the pixel deposition clock generation circuit for communicating the first clock source to the pixel deposition clock generation circuit, and a data output coupled to the bitmap data transfer circuit for communicating at least a portion of the raw digital data to the bitmap data transfer circuit; and
wherein the pixel deposition clock signal is generated from the first clock source by the pixel deposition clock generation circuit. - View Dependent Claims (11, 12, 13, 14)
a counter for generating a plurality of count values, having a clock input coupled to the clock output of the decoder circuit and a count value output;
a memory circuit having an internal look-up table, a count value input coupled to the count value output of the counter, and a voltage amplitude value output, the look-up table having a corresponding voltage amplitude value for each of the count values, and the memory circuit setting the voltage amplitude value output by consulting the look-up table for a voltage amplitude value corresponding to a count value received on the count value input; and
a digital-to-analog converter having a digital input coupled to the voltage amplitude value output of the memory circuit and a pixel deposition clock signal output.
-
-
14. The system of claim 13, wherein:
-
each of the pixel deposition clock generation circuits includes a preload register coupled to a preload input of the counter;
each of the print engine communication circuits includes a message processing circuit coupled to the data output of the decoder circuit, the message processing circuit monitoring the raw data and executing commands embedded in the raw data; and
the message processing circuit further updates the preload register as directed by one of the commands.
-
-
15. A high-speed printing system comprising:
-
a plurality of print engines;
a controller including a processing circuit for generating bitmap data, an output port, and an input port;
a plurality of print engine communication circuits, each of the communication circuits being operatively coupled to a corresponding one of the plurality of print engines, each of the communication circuits including an input port, an output port, a bitmap data transfer circuit, and a pixel deposition clock generation circuit for generating a pixel deposition clock signal for its the corresponding one of the print engines; and
a plurality of data links operatively coupling the print engine communication circuits to the controller;
wherein each of the bitmap data transfer circuits is coupled to the corresponding one of the plurality of print engines to provide the bitmap data to the corresponding one of the plurality of print engines, and each of the pixel deposition clock generation circuits is coupled to its the corresponding one of the print engines to provide a pixel deposition clock signal for the corresponding one of the plurality of print engines;
wherein the controller includes an encoder circuit, coupled to the output port of the controller, for encoding raw digital data and a first clock source into a data transmission code to be transmitted by the output port of the controller;
wherein each of the print engine communication circuits includes a decoder circuit for decoding the data transmission code back into the raw digital data and into the first clock source, the decoder circuit having a data input coupled to the input port of the print engine communication circuit, a clock output coupled to the pixel deposition clock generation circuit for communication the first clock source to the pixel deposition clock generation circuit, and a data output coupled to the bitmap data transfer circuit for communicating at least a portion of the raw digital data to the bitmap data transfer circuit; and
wherein each of the pixel deposition clock generation circuits generate the pixel deposition clock signal for the corresponding one of the plurality of print engines from the first clock source.
-
-
16. A method for synchronizing a plurality of pixel generation mechanisms on a corresponding plurality of print engines comprising the steps of:
-
communicating data to a plurality of print engines, by a printer controller, using a self-clocking data transmission code;
deriving a clock signal from the data by each of the print engines; and
each of the print engines driving a corresponding pixel deposition clock signal contained thereon using the clock signal.
-
-
17. A method for synchronizing a plurality of drive mechanisms on a corresponding plurality of print engines comprising the steps of:
-
providing a plurality of print engines, each of the print engines including a drive mechanism, the drive mechanism having a drive clock signal for controlling at least the speed of the drive mechanism;
embedding a first clock signal in data so as to produce a combined data and clock signal;
communicating the combined data and clock signal to each of the print engines;
deriving the first clock signal from the combined data and clock signal by each of the print engines; and
generating the drive clock signal for each of the drive mechanisms by each of the print engines. - View Dependent Claims (18)
transmitting the combined data and clock signal to a first one of the print engines in the print engine daisy chain; and
receiving and retransmitting the combined data and clock signal to a next one of the print engines in the print engine daisy-chain by the print engines until the combined data and clock signal is retransmitted to a last one of the print engines in the print engine daisy chain.
-
-
19. A high-speed printing system comprising:
-
a plurality of print engines;
a controller including a processing circuit for generating bitmap data, an output port, and an input port;
a plurality of print engine communication circuits, each of the communication circuits being operatively coupled to a corresponding one of the plurality of print engines, each of the communication circuits including an input port, an output port, a bitmap data transfer circuit, and a clock generation circuit for generating a synchrnozation clock signal for its the corresponding one of the print engines; and
a plurality of data links operatively coupling the print engine communication circuits to the controller;
wherein each of the bitmap data transfer circuits is coupled to the corresponding one of the plurality of print engines to provide the bitmap data to the corresponding one of the plurality of print engines, and each of the clock generation circuits is coupled to its the corresponding one of the print engines to provide a synchronization clock signal for the corresponding one of the plurality of print engines;
wherein the controller includes an encoder circuit, coupled to the output port of the controller, for encoding raw digital data and a first clock source into a data transmission code to be transmitted by the output port of the controller;
wherein each of the print engine communication circuits includes a decoder circuit for decoding the data transmission code back into the raw digital data and into the first clock source, the decoder circuit having a data input coupled to the input port of the print engine communication circuit, a clock output coupled to the clock generation circuit for communication the first clock source to the clock generation circuit, and a data output coupled to the bitmap data transfer circuit for communicating at least a portion of the raw digital data to the bitmap data transfer circuit; and
wherein each of the clock generation circuits generate the synchronization clock signal for the corresponding one of the plurality of print engines from the first clock source. - View Dependent Claims (20, 21, 22, 23)
-
Specification
-
- Resources
Litigation Campaign Assessment
Thank you for your request. You will receive a custom alert email when the Litigation Campaign Assessment is available.
×
Litigation Data
-
Current AssigneeForrest P. Gauthier
-
Original AssigneeTesseron Limited
-
InventorsGauthier, Forrest P., Jovic, Dimitrije L.
-
Primary Examiner(s)Coles, Edward
-
Assistant Examiner(s)EBRAHIMI DEHKORDY, SAEID
-
Application NumberUS09/316,552Time in Patent Office1,296 DaysField of Search358/1.15, 358/1.9, 358/358, 347/5.9, 347/10.75US Class Current358/1.15CPC Class CodesB41J 11/008 Controlling printhead for a...B41J 2/04505 aiming at correcting alignmentB41J 2/04541 Specific driving circuitB41J 2/04581 controlling heads based on ...H04N 1/40031 for a plurality of reproduc...
