Clock synchronous semiconductor memory device
DC
First Claim
Patent Images
1. A semiconductor device comprising:
- a plurality of input buffers of different types or configurations from each other and coupled to a common internal node; and
program circuitry for generating a signal setting one of said plurality of input buffers to an operable state, said plurality of input buffers driving the internal node according to a received signal when an input buffer is set to the operable state.
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Accused Products
Abstract
In a control circuit and an address buffer circuit, buffer circuits of plural types are provided to each of pin terminals and an input buffer of one type is activated according a state control signal group. In a standby state, current paths of the control buffer circuit and the address buffer circuit are selectively cut off according to a CS cut mode instructing signal stored in a mode register and an internal chip select signal. Furthermore, when a low power consumption mode is specified, a current path of a CLK buffer for generating an internal clock signal is cut off according to an external clock enable signal and a low power mode instructing signal, and the current paths of the control buffer circuit and the address buffer circuit are also cut-off.
29 Citations
20 Claims
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1. A semiconductor device comprising:
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a plurality of input buffers of different types or configurations from each other and coupled to a common internal node; and
program circuitry for generating a signal setting one of said plurality of input buffers to an operable state, said plurality of input buffers driving the internal node according to a received signal when an input buffer is set to the operable state. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 20)
said program circuitry comprises: a plurality of fuse circuits each including a fuse element selectively blown off and generating a signal corresponding to a blown off or conductive state of said fuse element; and
a decode circuit for decoding the output signals of said plurality of fuse circuits and generating a signal for controlling operation enabled and disabled states of the input buffers.
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4. The semiconductor device according to claim 1, wherein said program circuitry comprises a decode circuit for decoding voltage signals applied to a plurality of bonding pads set to respective prescribed voltage levels and generating a signal for controlling operation enabled and disabled states of the input buffers.
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5. The semiconductor device according to claim 1, further comprising:
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a register circuit for storing a data signal specifying whether control on an input buffer set to an operable state among said plurality of input buffers by an operation activating signal is valid, said operation activating signal indicating that an external signal applied to an input node provided corresponding to said plurality of input buffers is a valid signal; and
an activation control circuit for selectively activating said input buffer set to an operable state according to said operation activating signal and the stored data signal in said register circuit, said activation control circuit selectively activating said input buffer set to an operable state in accordance with said operation activating signal when the stored data signal indicating that the control on the input buffer set to an operable state by the activation control signal is valid, and rendering the plurality of input buffers operable in accordance with the signal programmed in said program circuitry when said stored signal in said register circuit indicates that control on said input buffer set to an operable state by said operation activating signal is invalid.
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6. The semiconductor device according to claim 5, wherein said semiconductor device is a synchronous semiconductor memory device operating in accordance with a clock signal, and
said operation activating signal is a chip select signal indicating that said semiconductor memory device is selected. -
7. The semiconductor device according to claim 1, further comprising:
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a next stage buffer circuit for further buffering the signal on said internal node;
a register circuit for storing a signal specifying whether control on said next stage buffer circuit by an operation activating signal is valid, said operation activating signal indicating that an external signal applied to a signal input node provided corresponding to said plurality of input buffers is a valid signal; and
an activation control circuit for selectively activating said next stage buffer circuit in accordance with said operation activating signal, said signal stored in said register circuit, and the signal programmed in said program circuit, said activation control circuit selectively activating said next stage buffer according to said operation activating signal when said signal stored in said register circuit indicates that control on said next stage buffer by said operation activating signal is valid, and setting said next stage buffer to an operating state all the times when said stored data in said register circuit indicates that control on said next stage buffer circuit by said operation activating signal is invalid.
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8. The semiconductor device according to claim 1, further comprising:
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a clock enable buffer for generating an internal clock enable signal according to an external clock enable signal;
a clock activation circuit for activating a clock activation signal in response to said internal clock enable signal and said external clock enable signal; and
a clock buffer for generating an internal clock signal according to an external clock signal when said clock activation signal is active, wherein the input buffer is set to a non-operating state when said internal clock enable signal is inactive, and said clock activation signal is activated after said external clock enable signal is held in an inactive state for a prescribed period of time.
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9. The semiconductor device according to claim 8, wherein said external enable clock signal is held at an inactive state in a low power operation mode, and the input buffer has an operation current flowing path cut off in response to inactivation of said internal clock enable signal.
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10. The semiconductor device according to claim 9, wherein
said semiconductor device is a clock synchronous semiconductor memory device operating in synchronization with said external clock signal, and said low power operation mode is an operation mode in which access to said semiconductor memory device is ceased. -
11. The semiconductor device according to claim 1, wherein said received signal comprises an externally applied signal.
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12. The semiconductor device according to claim 1, wherein said received signal comprises an externally applied signal and an internal control signal activating the input buffers.
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20. The semiconductor device according to claim 11, wherein said control circuitry deactivates said activation control signal according to said external clock enable signal when said external clock signal is at a first logical level.
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13. A semiconductor device comprising:
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signal input circuitry including an input buffer for buffering a signal provided externally and generating an internal signal when the signal input circuitry is active;
register circuitry for storing a signal specifying whether control on said signal input circuitry by an operation activation signal is valid, said operation activating signal indicating whether an external signal is a valid signal; and
an activation control circuit for selectively activating said signal input circuitry according to said operation activation signal and the signal stored in said register circuitry, said activation control circuit selectively activating said signal input circuitry according to said operation activation signal when the stored signal in said register circuitry indicates that control of activation and deactivation on said signal input circuitry by said operation activation signal is valid, and holding said signal input circuitry in an active state all the times when said stored signal in said register circuitry indicates that the control on said signal input circuitry by said operation activation signal is invalid. - View Dependent Claims (14, 15, 16)
said activation control circuit controls activation and deactivation of said next stage buffer circuit. -
16. The semiconductor device according to claim 13, wherein said semiconductor device is a synchronous semiconductor memory device operating according to a clock signal, and
said operation activating signal is a chip select signal indicating that said semiconductor memory device is selected.
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17. A semiconductor device comprising:
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a buffer circuit for buffering a signal provided externally when active;
a clock buffer for generating an internal clock signal according to an external clock signal when a clock enable signal is active;
clock detection circuitry for detecting whether said clock enable signal is held inactive for a prescribed period of time in a low power operation mode; and
control circuitry for setting said buffer circuit and said clock buffer to an inactive state in response to a detection signal of said clock detection circuitry. - View Dependent Claims (18, 19)
said low power operating mode is an operating mode in which access to said semiconductor memory device is ceased. -
19. The semiconductor device according to claim 17, wherein
said clock detection circuitry comprises a circuit for deactivating said detection signal in response to activation of an external clock enable signal, said control circuitry deactivates an activation control signal in response to said detection signal and activates said activation control signal in response to said external clock enable signal said external clock signal, and said buffer circuit and said clock buffer operate when said activation control signal is active and generate a corresponding internal signal according to a applied signal when active.
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Specification
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Litigation Data
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Current AssigneeLimestone Memory Systems LLC (Acacia Research Corporation)
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Original AssigneeRenesas Technology Corporation (Renesas Electronics Corporation)
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InventorsYamauchi, Tadaaki, Okamoto, Takeo, Matsumoto, Junko
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Primary Examiner(s)Lam, David
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Application NumberUS10/140,937Publication NumberTime in Patent Office656 DaysField of Search365/233, 365/225.7, 365/230.08, 365/189.05, 365/189.12, 365/226, 365/233.5US Class Current365/189.16CPC Class CodesG11C 11/4082 Address Buffers; level conv...G11C 7/1078 Data input circuits, e.g. w...G11C 7/1084 Data input buffers, e.g. co...G11C 7/109 Control signal input circuits
