Delay locked loop and locking method thereof

US 6,943,602 B1
Filed: 12/30/2004
Issued: 09/13/2005
Est. Priority Date: 10/29/2004
Status: Active Grant

- Alert
- Pin

First Claim

Patent Images

1. A delay locked loop with at least one delay line, comprising:

a buffering means for outputting a first clock corresponding to an in-phase of an external clock and outputting a second clock corresponding to an out-of-phase of the external clock;

a phase comparing means for outputting a control signal to increase/decrease a delay amount after comparing the first clock with a phase of a feedback clock;

a shift register for outputting a shift signal in accordance with the control signal;

a multiplexing means for selecting one between the first and the second clocks by using the output of the phase comparator and the output of the shift register.

View all claims

13 Assignments

Timeline View

Assignment View

Litigations

0 Petitions

Accused Products

Abstract

The present invention provides a delay locked loop of a semiconductor memory device for preventing a stuck fail. The DLL of the present invention includes: a buffer for outputting a first clock corresponding to an in-phase of an external clock and outputting a second clock corresponding to an out-of-phase of the external clock; a phase comparator for outputting a control signal to increase/decrease a delay amount after comparing the first clock with a phase of a feedback clock; a shift register for outputting a shift signal in accordance with the control signal; a multiplexing unit for selecting one between the first and the second clocks by using the output of the phase comparator and the output of the shift register.

57 Citations

View as Search Results

18 Claims

1. A delay locked loop with at least one delay line, comprising:
- a buffering means for outputting a first clock corresponding to an in-phase of an external clock and outputting a second clock corresponding to an out-of-phase of the external clock;
  
  a phase comparing means for outputting a control signal to increase/decrease a delay amount after comparing the first clock with a phase of a feedback clock;
  
  a shift register for outputting a shift signal in accordance with the control signal;
  
  a multiplexing means for selecting one between the first and the second clocks by using the output of the phase comparator and the output of the shift register.
- View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
- - 2. The delay locked loop as recited in claim 1, wherein the multiplexing means selects the second clock in case that the control signal to decrease the delay amount is inputted thereto when the first clock lags behind the feedback clock.
  - 3. The delay locked loop as recited in claim 1, wherein the multiplexing means selects the first clock in case that the control signal to increase the delay amount is inputted thereto when the second clock leads to the feedback clock.
  - 4. The delay locked loop as recited in claim 1, wherein the output of the shift register which is inputted into the multiplexing means is a maximum shift bit signal or a minimum shift bit signal.
  - 5. The delay locked loop as recited in claim 1, wherein the phase comparing means outputs the control signal to increase the delay amount when the first signal is in logic low level at a rising edge of the feedback clock, and outputs the control signal to decrease the delay amount when the first signal is in logic high level at a rising edge of the feedback clock.
  - 6. The delay locked loop as recited in claim 4, wherein the multiplexing means includes:
    - a multiplexer selector for outputting a selection signal to select one between the first and the second clocks by using the output of the phase comparator and the output of the shift register; and
      
      a multiplexer for outputting the selected one between the first and the second clocks of the buffer.
  - 7. The delay locked loop as recited in claim 6, wherein the multiplexer selector includes:
    - a first NAND gate for performing a logic NAND operation to the minimum shift bit signal and the command to decrease the delay amount;
      
      a second NAND gate for performing a logic NAND operation to the maximum shift bit signal and the command to increase the delay amount;
      
      a NOR gate for performing a logic NOR operation to the outputs of the first and the second NAND gates;
      
      a majority voter for outputting a predetermined signal when the output of the NOR gate is maintained for a predetermined time;
      
      a switch which is switched by the output of the majority voter and is reset by a reset signal; and
      
      a latch for latching the output of the switch.
  - 8. The delay locked loop as recited in claim 7, wherein the majority voter includes:
    - a first to a third D flip-flops which are connected in series for receiving the output of the NOR gate of the majority voter; and
      
      an AND gate for performing a logic AND operation to the first to the third D flip-flops.
  - 9. The delay locked loop as recited in claim 8, wherein the buffer includes:
    - a first input buffer for receiving the external clock signal though a positive terminal thereof and receiving an external clock bar signal through a negative terminal thereof; and
      
      a second input buffer for receiving the external clock signal though a negative terminal thereof and receiving the external clock bar signal through a positive terminal thereof.

10. A delay locked loop with at least one delay line, comprising:
- a buffering means for outputting a first clock corresponding to an in-phase of an external clock and outputting a second clock corresponding to an out-of-phase of the external clock;
  
  a phase comparing means for outputting a control signal to increase/decrease a delay amount after comparing a phase of the external clock with a phase of a feedback clock;
  
  a shift register for outputting a shift signal in accordance with the control signal;
  
  a multiplexing means for selecting one between the first and the second clocks by using the output of the phase comparator and the output of the shift register.
- View Dependent Claims (11, 12, 13, 14)
- - 11. The delay locked loop as recited in claim 10, wherein the multiplexing means selects the first clock in case that the control signal to increase the delay amount is inputted thereto when the second clock leads to the feedback clock.
  - 12. The delay locked loop as recited in claim 10, wherein the multiplexing means selects the first clock in case that the control signal to increase the delay amount is inputted thereto when the second clock leads to the feedback clock.
  - 13. The delay locked loop as recited in claim 10, wherein the multiplexing means includes:
    - a multiplexer selector for outputting a selection signal to select one between the first and the second clocks by using the output of the phase comparator and the output of the shift register; and
      
      a multiplexer for outputting the selected one between the first and the second clocks from the buffer.
  - 14. The delay locked loop as recited in claim 13, wherein the multiplexer selector includes:
    - a first NAND gate for performing a logic NAND operation to the minimum shift bit signal and the command to decrease the delay amount;
      
      a second NAND gate for performing a logic NAND operation to the maximum shift bit signal and the command to increase the delay amount;
      
      a NOR gate for performing a logic NOR operation to the outputs of the first and the second NAND gates;
      
      a majority voter for outputting a predetermined signal when the output of the NOR gate is maintained for a predetermined time;
      
      a switch which is switched by the output of the majority voter and is reset by a reset signal; and
      
      a latch for latching the output of the switch.

15. A locking method of a delay locked loop with at least one delay line, comprising the steps of:
- a) outputting a first clock corresponding to an in-phase of an external clock and a second clock corresponding to an out-of-phase of the external clock;
  
  b) outputting a command to increase or decrease a delay amount by comparing a phase of the external clock with a phase of a feedback clock;
  
  c) outputting a shift signal in accordance with the command to increase or decrease the delay amount; and
  
  d) selecting one clock between the first and the second clocks by using the command and the shift signal.
- View Dependent Claims (16, 17, 18)
- - 16. The locking method as recited in claim 15, wherein the step d) is performed to select the other clock in case that the command to decrease the delay amount is inputted when a phase of one of the first and the second clock passing through the delay line is delayed minimally.
  - 17. The locking method as recited in claim 15, wherein the step d) is performed to select the other clock in case that the command to increase the delay amount is inputted when a phase of one of the first and the second clock passing through the delay line is delayed maximally.
  - 18. The locking method as recited in claim 15, wherein the step d) includes the steps of:
    - d1) outputting a selection signal for selecting one of the first and the second clocks by using the command and the shift signal; and
      
      d2) outputting the selected one of the first and the second clocks controlled by a control signal.

Specification

Resources

Litigation Campaign Assessment

Litigation Data

Current Assignee
Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
Original Assignee
Hynix Semiconductor Incorporated (SK Hynix Inc.)
Inventors
Lee, Hyun-Woo
Primary Examiner(s)
Callahan, Timothy P.
Assistant Examiner(s)
Cox, Cassandra

Application Number

US11/026,970
Time in Patent Office

257 Days
Field of Search

327/141, 327/147, 327/149, 327/152, 327/153, 327/158, 327/161
US Class Current

327/158
CPC Class Codes

H03L 7/0814   the phase shifting device b...

H03L 7/0816   the controlled phase shifte...

H03L 7/089   the phase or frequency dete...

Delay locked loop and locking method thereof

First Claim

13 Assignments

Litigations

0 Petitions

Accused Products

Abstract

57 Citations

18 Claims

Specification

Use Cases

Quick Links

Others

Delay locked loop and locking method thereof

First Claim

13 Assignments

Subscription Required

Subscription Required

Litigations

0 Petitions

Subscription Required

Accused Products

Subscription Required

Abstract

57 Citations

18 Claims

Specification

Subscription Required

Use Cases

Quick Links

Others