Automated wear leveling in non-volatile storage systems
DCFirst Claim
1. In a memory system including a plurality of units of erasable and re-programmable non-volatile memory cells having contiguous physical addresses organized into zones with address boundaries therebetween and wherein a distinct range of logical addresses are mapped into each of the zones, a method of operation that comprises:
- reassigning the boundary addresses to delete at least one unit from each of the zones and to add said at least one unit to an adjacent zone without changing the number of units in the individual zones,thereafter accessing the zones for programming data to or reading data from the reassigned memory cell units therein according to logical addresses of the data, andrepetitively reassigning the boundary addresses and accessing the zones at least until the plurality of memory cell units have all been moved from their zones to adjacent zones, thereby to spread out usage of the units accessed through the logical addresses.
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Accused Products
Abstract
Methods and apparatus for performing wear leveling in a non-volatile memory system are disclosed. Included is a method for performing wear leveling in a memory system that includes a first zone, which has a first memory element that includes contents, and a second zone includes identifying the first memory element and associating the contents of the first memory element with the second zone while disassociating the contents of the first memory element from the first zone. In one embodiment, associating the contents of the first memory element with the second involves moving contents of a second memory element into a third memory element, then copying the contents of the first memory element into the second memory element.
295 Citations
28 Claims
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1. In a memory system including a plurality of units of erasable and re-programmable non-volatile memory cells having contiguous physical addresses organized into zones with address boundaries therebetween and wherein a distinct range of logical addresses are mapped into each of the zones, a method of operation that comprises:
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reassigning the boundary addresses to delete at least one unit from each of the zones and to add said at least one unit to an adjacent zone without changing the number of units in the individual zones, thereafter accessing the zones for programming data to or reading data from the reassigned memory cell units therein according to logical addresses of the data, and repetitively reassigning the boundary addresses and accessing the zones at least until the plurality of memory cell units have all been moved from their zones to adjacent zones, thereby to spread out usage of the units accessed through the logical addresses. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method of operating a system of erasable and re-programmable non-volatile memory cells that are physically organized into units of a minimum number of memory cells that are simultaneously erasable, comprising:
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directing host access requests to program or read data within one of three or more non-overlapping ranges of logical memory addresses into a unique one of a corresponding number of logical groups of memory cell erase units, mapping access requests from the logical groups into distinct physical groups of a plurality of erase units, and between data programming or reading operations caused by host access requests, repetitively re-mapping the logical groups into the physical groups by removing a portion of the individual physical groups including at least one erase unit at a time and adding the removed erase units to adjacent ones of the physical groups in a manner that maintains a uniform number of erase units in the individual physical groups, whereby usage of the erase units over the system is leveled out over time.
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8. A method of operating an array of flash memory cells organized into a plurality of blocks of a minimum number of simultaneously erasable memory cells within a plurality of planes, comprising:
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defining a plurality of zones to individually include a portion of the plurality of blocks from each of a plurality of planes, mapping a different portion of a range of logical addresses to each of the zones, and repetitively re-defining the individual zones by removing at least one block therefrom in each plane and adding the removed blocks to others of the zones in their same planes in a manner to maintain the plurality of zones with the specified plurality of blocks in each of the plurality of planes, whereby usage of the blocks at various of the ranges of logical addresses is spread out in time over the array.
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9. In a memory system including a plurality of zones individually including a plurality of units of re-programmable non-volatile memory cells that are erasable together, wherein a distinct range of logical addresses received by the memory system are mapped into the individual zones, a method of operation that comprises:
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receiving a logical address within the distinct logical address range of one of the zones, and converting the received logical address into a physical address of at least one of the plurality of memory cell erase units within said one zone that tends to even out a number of usage cycles of erasing and re-programming the erase units within said one zone. - View Dependent Claims (10, 11, 12)
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13. In a memory system including a plurality of zones individually including a plurality of units of re-programmable non-volatile memory cells that are erasable together, wherein a distinct range of logical addresses received by the memory system are mapped into the individual zones, a method of operation that comprises:
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exchanging data stored in a first of the plurality of zones with data stored in a second of the plurality of zones, and thereafter converting addresses accessing the memory system within one of the first and second zones to addresses accessing the other of the first and second zones. - View Dependent Claims (14)
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15. A method of operating a system of erasable and re-programmable non-volatile memory cells organized into a plurality of physical blocks of a minimum number of memory cells that are simultaneously erasable and wherein incoming data are programmed into those of the plurality of physical blocks maintained as an erased block pool, comprising:
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identifying at least one of the plurality of physical blocks at a time other than those in the erased block pool for a wear leveling exchange by cycling through addresses of the plurality of physical blocks in a predefined order, and exchanging the identified at least one of the plurality of physical blocks with a corresponding number of at least one of the plurality of physical blocks within the erased block pool. - View Dependent Claims (16, 17, 18, 19)
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20. A method of operating a system of erasable and re-programmable non-volatile memory cells organized into a plurality of physical blocks of a minimum number of memory cells that are simultaneously erasable, comprising:
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mapping a range of logical block addresses into addresses of a proportion of the plurality of physical blocks that leaves an additional number of physical blocks providing an erased block pool, in response to requests to store data in at least one of the range of logical block addresses, converting said at least one logical block address into an address of at least one physical block residing in the erased block pool and then writing the data into said at least one physical block of the erased block pool, identifying one of the plurality of physical blocks for a wear leveling exchange, after a given number of memory programming operations, exchanging the identified one of the plurality of physical blocks with one of the number of physical blocks residing in the erased block pool, and repeating identifying and exchanging with others of the plurality of physical blocks in a predefined order. - View Dependent Claims (21, 22, 23)
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24. A method of managing a plurality of groups of erasable and electrically programmable memory cells, comprising:
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upon programming data into ones of the plurality of groups of cells, associating and storing one of a plurality of indications for the individual programmed groups of cells that is selected by incrementing the indication after a predefined number of instances of programming of ones of the plurality of groups have occurred, the associated and stored indications being repetitively incremented through the plurality of indications in a predefined order, wherein the stored indications provide relative times of programming of the corresponding groups of cells, and performing an operation on the groups of memory cells according to their relative numbers assigned. - View Dependent Claims (25, 26, 27, 28)
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Specification