Three dimensional structure integrated circuit

DC CAFC

US 7,193,239 B2
Filed: 07/03/2003
Issued: 03/20/2007
Est. Priority Date: 04/04/1997
Status: Expired due to Term

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First Claim

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1. Circuitry comprising:

a plurality of monolithic substrates having integrated circuits formed thereon and stacked in layers such that each layer comprises only one of the substrates, wherein at least one of the plurality of substrates is a substantially flexible substrate, and wherein a major portion of the monolithic substrate is removed; and

between adjacent substrates, a bonding layer bonding together the adjacent substrates, the bonding layer being formed by bonding first and second substantially planar surfaces having a bond-forming material throughout a majority of the surface area thereof.

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Abstract

A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

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79 Claims

1. Circuitry comprising:
- a plurality of monolithic substrates having integrated circuits formed thereon and stacked in layers such that each layer comprises only one of the substrates, wherein at least one of the plurality of substrates is a substantially flexible substrate, and wherein a major portion of the monolithic substrate is removed; and
  
  between adjacent substrates, a bonding layer bonding together the adjacent substrates, the bonding layer being formed by bonding first and second substantially planar surfaces having a bond-forming material throughout a majority of the surface area thereof.
- View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
- - 2. The apparatus of claim 1, further comprising vertical interconnects having vertical interconnect segments formed of a first metal contact on a first substrate bonded to a second aligned metal contact on a second adjacent substrate.
  - 3. The apparatus of claim 2, wherein the plurality of aligned vertical interconnect segments are joined to form a vertical interconnect between non-adjacent substrates.
  - 4. The apparatus of claim 1, wherein at least one of said substrates is a substantially rigid substrate having a first thickness.
  - 5. The apparatus of claim 4, wherein a plurality of substrates have a reduced second thickness substantially less than said first thickness.
  - 6. The apparatus of claim 5, wherein a ratio of said first thickness to said second thickness is approximately 10:
    - 1.
  - 7. The apparatus of claim 5, wherein a ratio of said first thickness to said second thickness is at least 10:
    - 1.
  - 8. The apparatus of claim 1, further comprising vertical interconnects formed between the adjacent bonded substrates to interconnect the integrated circuits in subsequent processing steps.
  - 9. The apparatus of claim 1, further comprising vertical interconnects formed between the adjacent bonded substrates to interconnect the integrated circuits in subsequent processing steps.
  - 10. The apparatus of claim 1, wherein the circuitry is formed with a low stress dielectric.
  - 11. The apparatus of claim 10, wherein the low stress dielectric is at least one of a silicon dioxide dielectric, an oxide of silicon dielectric, and caused to have stress of about 5×
    - 10⁸dynes/cm²or less.
  - 12. The apparatus of claim 11, wherein the stress of the low stress dielectric is tensile.

13. An integrated circuit structure comprising:
- a first substrate having a first surface; and
  
  a second substrate bonded to the first surface of the first substrate to form conductive paths between the first substrate and the second substrate wherein the second substrate is a substantially flexible monolithic monocrystalline semiconductor substrate having active circuitry formed thereon, wherein no other substrates are bonded to the first surface, and wherein a major portion of the second substantially flexible monolithic monocrystalline semiconductor substrate is removed.
- View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
- - 14. The apparatus of claim 13, wherein the first substrate having polycrystalline active circuitry formed thereon.
  - 15. The apparatus of claim 13, wherein the first substrate having active circuitry formed thereon.
  - 16. The apparatus of claim 13, wherein at least one of the first and second substrates having passive circuitry formed thereon.
  - 17. The apparatus of claim 13, wherein at least one of the first substrate and the second substrate is a thinned substantially flexible substrate.
  - 18. The apparatus of claim 13, further comprising a low stress dielectric layer overlying at least one of the first substrate and the second substrate.
  - 19. The apparatus of claim 18, wherein the low stress dielectric layer is at least one of a silicon dioxide dielectric, an oxide of silicon dielectric, and caused to have a stress of about 5×
    - 10⁸dynes cm²or less.
  - 20. The apparatus of claim 19, wherein the stress of the low stress dielectric is tensile.
  - 21. The apparatus of claim 13, wherein at least one substrate of the first and second substrates has memory circuitry formed thereon and at least one of the first and second substrates has logic circuitry formed thereon, wherein the at least one substrate that has logic circuitry formed thereon performs programmable gate line address assignment with respect to the at least one substrate that has memory circuitry formed thereon.
  - 22. The apparatus of claim 13, wherein information processing is performed on data routed between the first and second substrates.
  - 23. The apparatus of claim 13, wherein at least one substrate of the first and second substrates has logic circuitry formed thereon for performing at least one function from the group consisting of:
    - virtual memory management, ECC, indirect addressing, content addressing, data compression, data decompression, graphics acceleration, audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, power management and database processing.

24. A stacked integrated circuit comprising:
- a plurality of integrated circuit substrates having formed on corresponding surfaces thereof complementary patterns of a material bondable using thermal diffusion bonding, wherein at least one of the plurality of substrates is a substantially flexible monolithic integrated circuit substrate, and wherein a major portion of the at least one substantially flexible monolithic integrated circuit substrate is removed; and
  
  a thermal diffusion bonded region between the complementary patterns.
- View Dependent Claims (25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43)
- - 25. The apparatus of claim 24, wherein at least one integrated circuit substrate of the plurality of integrated circuit substrates has memory circuitry formed thereon, the memory circuitry having a plurality of memory locations including at least one memory location used for sparing, wherein data from the at least one memory location on the at least one integrated circuit substrate that has memory circuitry formed thereon is used instead of data from a defective memory location on the at least one integrated circuit substrate that has memory circuitry formed thereon.
  - 26. The apparatus of claim 24, wherein at least one integrated circuit substrate of the plurality of integrated circuit substrates has memory circuitry formed thereon and at least one integrated circuit substrate of the plurality of integrated circuit substrates has logic circuitry formed thereon, wherein the at least one integrated circuit substrate that has logic circuitry formed thereon performs programmable gate line address assignment with respect to the at least one integrated circuit substrate that has memory circuitry formed thereon.
  - 27. The apparatus of claim 24, wherein information processing is performed on data routed between circuitry of at least two of the plurality of integrated circuit substrates.
  - 28. The apparatus of claim 24, wherein at least one integrated circuit substrate of the plurality of integrated circuit substrates has reconfiguration circuitry.
  - 29. The apparatus of claim 24, wherein at least one integrated circuit substrate of the plurality of integrated circuit substrates has logic circuitry formed thereon for performing at least one function from the group consisting of:
    - virtual memory management, ECC, indirect addressing, content addressing, data compression, data decompression, graphics acceleration, audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, power management and database processing.
  - 30. The apparatus of claim 24, further comprising:
    - a memory array having a plurality of memory storage cells, a plurality of data lines, and a plurality of gate lines, each memory storage cell stores a data value and has circuitry for coupling that data value to one of the plurality of data lines in response to receiving a gate control signal from one of the plurality of gate lines;
      
      circuitry that generates the gate control signal in response to receiving an address, including means for mapping addresses to gate lines; and
      
      a controller that determines if one of the plurality of memory cells is defective and alters the mapping to eliminate references to the one of the plurality of memory cells that is defective.
  - 31. The apparatus of claim 24, further comprising:
    - at least one controller substrate having logic circuitry formed thereon;
      
      at least one memory substrate having memory circuitry formed thereon;
      
      a plurality of data lines and a plurality of gate lines on each memory substrate;
      
      an array of memory cells on each memory substrate, each memory cell stores a data value and has circuitry that couples the data value to one of the plurality of data lines in response to selecting of one of the plurality of gate lines;
      
      a gate line selection circuit that enables a gate line for a memory operation, wherein the gate line selection circuit has programmable gates to receive address assignments for at least one of the plurality of gate lines and wherein the address assignments for determining which of the plurality of gate lines is selected for each programmed address assignment; and
      
      controller substrate logic that determines if one memory cell of the array of memory cells is defective and alters the address assignments of the plurality of gate lines to remove references to the gate line that causes the defective memory cell to couple a data value to one of the plurality of data lines.
  - 32. The apparatus of claim 31, wherein said controller substrate logic:
    - tests the array of memory cells periodically to determine if one of said memory cells is defective; and
      
      removes references in the address assignments to gate lines that cause detected defective memory cells to couple data values to the plurality of data lines.
  - 33. The apparatus of claim 31, further comprising programmable logic to prevent the use of data values from the plurality of data lines when gate lines cause detected defective memory cells to couple data values to the plurality of data lines.
  - 34. The apparatus of claim 31, wherein the array of memory cells are arranged within physical space in a physical order and are arranged within an address space in a logical order, wherein the physical order of at least one memory cell is different than the logical order of the at least one memory cell.
  - 35. The apparatus of claim 31, wherein:
    - the logic circuitry of the at least one controller substrate is tested by an external means; and
      
      the array of memory cells of the at least one memory substrate are tested by the logic circuitry of the at least one controller substrate, wherein the testing achieves a functional testing of a substantial portion of the array of memory cells.
  - 36. The apparatus of claim 31, wherein the logic circuitry of the at least one controller substrate performs functional testing of a substantial portion of the array of memory cells.
  - 37. The apparatus of claim 31, wherein the controller substrate logic is further configured to:
    - prevent the use of at least one defective gate line; and
      
      replace references to memory cells addressed using the defective gate line with references to spare memory cells addressed using a spare gate line.
  - 38. The apparatus of claim 31, wherein the controller substrate logic is further configured to prevent the use of at least one defective gate line.
  - 39. The apparatus of claim 31, wherein the logic circuitry of the at least one controller substrate performs all functional testing of the array of memory cells of the at least one memory substrate.
  - 40. The apparatus of claim 24, wherein at least one of the plurality of integrated circuit substrates is a thinned substantially flexible substrate.
  - 41. The apparatus of claim 24, wherein at least one of the plurality of integrated circuit substrates is formed with a low stress dielectric.
  - 42. The apparatus of claim 41, wherein the low stress dielectric is at least one of a silicon dioxide dielectric, an oxide of silicon dielectric, and caused to have a stress of about 5×
    - 10⁸dynes/cm²or less.
  - 43. The apparatus of claim 42, wherein the stress of the low stress dielectric is tensile.

44. An integrated circuit structure comprising:
- a first substrate having a first surface; and
  
  a second substrate bonded to the first surface of the first substrate to form conductive paths between the first substrate and the second substrate wherein the second substrate is a substantially flexible monolithic monocrystalline semiconductor substrate having active circuitry formed thereon, wherein no other substrates are bonded to the first surface, wherein at least one substrate of the first and second substrates has memory circuitry formed thereon, the memory circuitry having a plurality of memory locations including at least one memory location used for sparing, wherein data from the at least one memory location on the at least one substrate that has memory circuitry formed thereon is used instead of data from a defective memory location on the at least one substrate that has memory circuitry formed thereon.
- View Dependent Claims (45)
- - 45. The apparatus of claim 44, further comprising at least one dielectric layer wherein the dielectric layer comprises at least one of a silicon dioxide dielectric, an oxide of silicon dielectric, and a dielectric with a tensile stress of 5×
    - 10⁸dynes/cm²or less.

46. An integrated circuit structure comprising:
- a first substrate having a first surface; and
  
  a second substrate bonded to the first surface of the first substrate to form conductive paths between the first substrate and the second substrate wherein the second substrate is a substantially flexible monolithic monocrystalline semiconductor substrate having active circuitry formed thereon, wherein no other substrates are bonded to the first surface, wherein at least one substrate of the first and second substrates has reconfiguration circuitry.
- View Dependent Claims (47)
- - 47. The apparatus of claim 46, further comprising at least one dielectric layer wherein the dielectric layer comprises at least one of a silicon dioxide dielectric, an oxide of silicon dielectric, and a dielectric with a tensile stress of 5×
    - 10⁸dynes/cm²or less.

48. An integrated circuit structure comprising:
- a first substrate having a first surface; and
  
  a second substrate bonded to the first surface of the first substrate to form conductive paths between the first substrate and the second substrate wherein the second substrate is a substantially flexible monolithic monocrystalline semiconductor substrate having active circuitry formed thereon, wherein no other substrates are bonded to the first surface;
  
  a memory array having a plurality of memory storage cells, a plurality of data lines, and a plurality of gate lines, each memory storage cell stores a data value and has circuitry for coupling that data value to one of the plurality of data lines in response to receiving a gate control signal from one of the plurality of gate lines;
  
  circuitry that generates the gate control signal in response to receiving an address, including means for mapping addresses to gate lines; and
  
  a controller that determines if one of the plurality of memory cells is defective and alters the mapping to eliminate references to the one of the plurality of memory cells that is defective.
- View Dependent Claims (49)
- - 49. The apparatus of claim 48, further comprising at least one dielectric layer wherein the dielectric layer comprises at least one of a silicon dioxide dielectric, an oxide of silicon dielectric, and a dielectric with a tensile stress of 5×
    - 10⁸dynes/cm²or less.

50. An integrated circuit structure comprising:
- a first substrate having a first surface; and
  
  a second substrate bonded to the first surface of the first substrate to form conductive paths between the first substrate and the second substrate wherein the second substrate is a substantially flexible monolithic monocrystalline semiconductor substrate having active circuitry formed thereon, wherein no other substrates are bonded to the first surface;
  
  at least one controller substrate having logic circuitry formed thereon;
  
  at least one memory substrate having memory circuitry formed thereon;
  
  a plurality of data lines and a plurality of gate lines on each memory substrate;
  
  an array of memory cells on each memory substrate, each memory cell stores a data value and has circuitry that couples the data value to one of the plurality of data lines in response to selecting of one of the plurality of gate lines;
  
  a gate line selection circuit that enables a gate line for a memory operation, wherein the gate line selection circuit has programmable gates to receive address assignments for at least one of the plurality of gate lines and wherein the address assignments for determining which of the plurality of gate lines is selected for each programmed address assignment; and
  
  controller substrate logic that determines if one memory cell of the array of memory cells is defective and alters the address assignments of the plurality of gate lines to remove references to the gate line that causes the defective memory cell to couple a data value to one of the plurality of data lines.
- View Dependent Claims (51, 52, 53, 54, 55, 56, 57, 58, 59)
- - 51. The apparatus of claim 50, wherein said controller substrate logic:
    - tests the array of memory cells periodically to determine if one of said memory cells is defective; and
      
      removes references in the address assignments to gate lines that cause detected defective memory cells to couple data values to the plurality of data lines.
  - 52. The apparatus of claim 50, further comprising programmable logic to prevent the use of data values from the plurality of data lines when gate lines cause detected defective memory cells to couple data values to the plurality of data lines.
  - 53. The apparatus of claim 50, wherein the array of memory cells are arranged within physical space in a physical order and are arranged within an address space in a logical order, wherein the physical order of at least one memory cell is different than the logical order of the at least one memory cell.
  - 54. The apparatus of claim 50, wherein:
    - the logic circuitry of the at least one controller substrate is tested by an external means; and
      
      the array of memory cells of the at least one memory substrate are tested by the logic circuitry of the at least one controller substrate, wherein the testing achieves a functional testing of a substantial portion of the array of memory cells.
  - 55. The apparatus of claim 50, wherein the logic circuitry of the at least one controller substrate performs functional testing of a substantial portion of the array of memory cells.
  - 56. The apparatus of claim 50, wherein the controller substrate logic is further configured to:
    - prevent the use of at least one defective gate line; and
      
      replace references to memory cells addressed using the defective gate line with references to spare memory cells addressed using a spare gate line.
  - 57. The apparatus of claim 50, wherein the controller substrate logic is further configured to prevent the use of at least one defective gate line.
  - 58. The apparatus of claim 50, wherein the logic circuitry of the at least one controller substrate performs all functional testing of the array of memory cells of the at least one memory substrate.
  - 59. The apparatus of claim 50, further comprising at least one dielectric layer wherein the dielectric layer comprises at least one of a silicon dioxide dielectric, an oxide of silicon dielectric, and a dielectric with a tensile stress of 5×
    - 10⁸dynes/cm²or less.

60. An integrated circuit structure comprising:
- a plurality of semiconductor dice, each die having an integrated circuit formed thereon, said dice being stacked in layers, wherein at least one of the plurality of dice is substantially flexible, and wherein at least one of the plurality of dice has at least one of polycrystalline active circuitry formed thereon, reconfiguration circuitry formed thereon, and passive circuitry formed thereon; and
  
  between adjacent dice, a bonding layer bonding together the adjacent dice, the bonding layer bonding first and second substantially planar adjacent surfaces of the adjacent dice, with at least one or more portions of the bonding layer being located other than at the edges of the adjacent dice.
- View Dependent Claims (61, 62, 63, 64, 65, 66, 67, 68, 69)
- - 61. The apparatus of claim 60, wherein at least one integrated circuit of the plurality of dice is formed with a low stress dielectric.
  - 62. The apparatus of claim 61, wherein the low stress dielectric is at least one of a silicon dioxide dielectric, an oxide of silicon dielectric, and caused to have stress of about 5×
    - 10⁸dynes/cm²or less.
  - 63. The apparatus of claim 62, wherein the stress of the low stress dielectric is tensile.
  - 64. The apparatus of claim 60, wherein at least one of the plurality of dice has a substrate, wherein at least one of a major portion of the substrate is removed and a major portion of the substrate is able to be removed while retaining the structural integrity of the integrated circuit formed on the substrate.
  - 65. The apparatus of claim 60, wherein at least one of the plurality of dice is a substantially rigid substrate having a first thickness.
  - 66. The apparatus of claim 65, wherein at least one of the plurality of dice has a second thickness, wherein the second thickness is substantially less than the first thickness.
  - 67. The apparatus of claim 60, further comprising at least one of interconnects formed between adjacent bonded surfaces of adjacent dice and wire interconnects formed between the dice.
  - 68. The apparatus of claim 60, wherein information processing is performed on data routed between any two of the plurality of dice.
  - 69. The apparatus of claim 60, wherein the at least one or more portions of the bonding layer include one portion located substantially close to the centers of the substantially planar adjacent surfaces of the adjacent dice.

70. An integrated circuit structure comprising:
- a substrate having a first surface; and
  
  a semiconductor die having an integrated circuit formed thereon bonded to the first surface of the substrate with conductive paths between the substrate and the die wherein the die is substantially flexible, wherein the semiconductor die is attached to the first surface of the substrate by one or more bonds including one bond located other than at the edges of the semiconductor die, and wherein at least one of the substrate and die has at least one of polycrystalline active circuitry formed thereon, reconfiguration circuitry formed thereon, and passive circuitry formed thereon.
- View Dependent Claims (71, 72, 73, 74, 75, 76, 77, 78, 79)
- - 71. The apparatus of claim 70, wherein the integrated circuit is formed with a low stress dielectric.
  - 72. The apparatus of claim 71, wherein the low stress dielectric is at least one of a silicon dioxide dielectric, an oxide of silicon dielectric, and caused to have stress of about 5×
    - 10⁸dynes/cm²or less.
  - 73. The apparatus of claim 72, wherein the stress of the low stress dielectric is tensile.
  - 74. The apparatus of claim 70, wherein the substrate having circuitry formed thereon.
  - 75. The apparatus of claim 70, wherein the substrate is formed from a non-semiconductor material.
  - 76. The apparatus of claim 70, wherein the die has a substrate, wherein at least one of a major portion of the substrate of the die is removed and a major portion of the die is able to be removed while retaining the structural integrity of the integrated circuit formed on the die.
  - 77. The apparatus of claim 70, wherein the conductive paths are at least one of wire interconnects and interconnects formed on the bonded surfaces between the substrate and the die.
  - 78. The apparatus of claim 70, wherein information processing is performed on data routed between the substrate and the die.
  - 79. The apparatus of claim 70, wherein the integrated circuit bond location is substantially close to the center of the semiconductor die.

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Litigation Data

Current Assignee
Elm 3DS Innovations LLC
Original Assignee
ELM TECHNOLOGY CORPORATION
Inventors
Leedy, Glenn J
Primary Examiner(s)
Smith, Zandra V.
Assistant Examiner(s)
Perkins, Pamela E

Application Number

US10/614,067
Publication Number

US 20040097008A1
Time in Patent Office

1,356 Days
Field of Search

257/74, 257/686, 257/723, 257/724, 438/17, 438/18, 438/123, 714/30, 714/718, 714/719
US Class Current

257/74
CPC Class Codes

G11C 29/44   Indication or identificatio...

G11C 29/81   using a hierarchical redund...

G11C 29/846   by choosing redundant lines...

G11C 29/848   by adjacent switching

G11C 5/02   Disposition of storage elem...

G11C 5/025   Geometric lay-out considera...

G11C 5/04   Supports for storage elemen...

H01L 2224/29109   Indium [In] as principal co...

H01L 2224/29111   Tin [Sn] as principal const...

H01L 2224/29116   Lead [Pb] as principal cons...

H01L 2224/29118   Zinc [Zn] as principal cons...

H01L 2224/29124   Aluminium [Al] as principal...

H01L 2224/29144   Gold [Au] as principal cons...

H01L 2224/29147   Copper [Cu] as principal co...

H01L 2224/29155   Nickel [Ni] as principal co...

H01L 2224/29166   Titanium [Ti] as principal ...

H01L 2224/29169   Platinum [Pt] as principal ...

H01L 2224/8083   Solid-solid interdiffusion

H01L 2225/06541   Conductive via connections ...

H01L 23/481   Internal lead connections, ...

H01L 25/18 : the devices being of types ...

H01L 27/0688 : Integrated circuits having ...

H01L 27/105 : including field-effect comp...

H01L 2924/00014 : the subject-matter covered ...

H01L 2924/01079 : Gold [Au]

H10B 12/50 : Peripheral circuit region s...

Y10S 438/977 : Thinning or removal of subs...

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Three dimensional structure integrated circuit

First Claim

4 Assignments

Litigations

2 Petitions

Accused Products

Abstract

356 Citations

79 Claims

Specification

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Three dimensional structure integrated circuit

First Claim

4 Assignments

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Litigations

2 Petitions

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Accused Products

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Abstract

356 Citations

79 Claims

Specification

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Solutions

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