Flash memory data correction and scrub techniques
DC
First Claim
Patent Images
1. A non-volatile memory system, comprising:
- an array of flash memory cells organized into blocks of a minimum number of memory cells that are erasable together and the blocks individually storing a plurality of units of data, anda controller coupled with the memory cell array and that operates to;
identify when a scrub trigger event has occurred for data stored in at least one of the units of data in a first one of the blocks,read the identified at least one unit of data from the first block,correct any errors in the data read from the first block to provide corrected first block data,write the corrected first block data as at least one unit of data to a second one of the blocks, andthereafter copy uncorrected data units of the first block into the second block, thereby to consolidate in the second block corrected and uncorrected units of data originally of the first block.
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Litigations
1 Petition
Accused Products
Abstract
In order to maintain the integrity of data stored in a flash memory that are susceptible to being disturbed by operations in adjacent regions of the memory, disturb events cause the data to be read, corrected and re-written before becoming so corrupted that valid data cannot be recovered. The sometimes conflicting needs to maintain data integrity and system performance are balanced by deferring execution of some of the corrective action when the memory system has other high priority operations to perform. In a memory system utilizing very large units of erase, the corrective process is executed in a manner that is consistent with efficiently rewriting an amount of data much less than the capacity of a unit of erase.
193 Citations
28 Claims
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1. A non-volatile memory system, comprising:
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an array of flash memory cells organized into blocks of a minimum number of memory cells that are erasable together and the blocks individually storing a plurality of units of data, and a controller coupled with the memory cell array and that operates to; identify when a scrub trigger event has occurred for data stored in at least one of the units of data in a first one of the blocks, read the identified at least one unit of data from the first block, correct any errors in the data read from the first block to provide corrected first block data, write the corrected first block data as at least one unit of data to a second one of the blocks, and thereafter copy uncorrected data units of the first block into the second block, thereby to consolidate in the second block corrected and uncorrected units of data originally of the first block. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A non-volatile memory system, comprising:
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an array of flash memory cells, and a controller coupled with the memory cell array and that operates to; identify when a scrub trigger event has occurred for data stored in at least one location of the array, read the data stored in said at least one location in the array, temporarily store information about said at least one location and the data read therefrom, while this information remains stored, program or read other data to or from at least locations within the array other than said at least one location, thereafter determine whether there are any errors in the data read from said at least one location in the array, utilize the stored information to correct any errors in the data read from said at least one location in the array, and write the corrected data into the array. - View Dependent Claims (8)
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9. A non-volatile memory system, comprising:
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an array of flash memory cells, a controller coupled with the memory cell array and that operates to; identify when a scrub trigger event has occurred for data stored in at least one location of the array, read the data stored in said at least one location in the array, thereafter determine whether there are any errors in the data read from said at least one location in the array, correct any errors in the data read from said at least one location in the array, temporarily store the corrected data, while the corrected data remain temporarily stored, program or read other data to or from at least locations within the array other than said at least one location, and thereafter writing the corrected data into the memory cell array. - View Dependent Claims (10)
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11. A memory system, comprising:
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an array of erasable and re-programmable non-volatile memory cells organized into blocks of a minimum number of memory cells that are erasable together and that individually include a plurality of pages which individually store one or more units of data, a controller coupled with the memory cell array and that operates to; in response to the occurrence of at least one of a plurality of predefined events, identify at least one page of at least one block to be scrubbed, read data stored in said at least one page with a first set of read conditions, determine whether there are any errors in the read data, and, if so, whether the errors can be corrected, in response to determining that the errors in the read data cannot be corrected, re-read the data stored in said at least one page with a second set of read conditions, determine whether there are any errors in the re-read data, and, if so, whether the errors can be corrected, in response to other memory activity being scheduled, deferr further action with respect to the read or re-read data, after the other memory activity is completed and in response to determining that the errors in either of the read or re-read data can be corrected, correct such errors to provide corrected data, and write the corrected data into at least a second page of a second block different from said one block. - View Dependent Claims (12)
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13. A memory system, comprising:
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a plurality of groups of re-programmable non-volatile memory cells that store data as levels of charge therein, wherein the groups individually store a plurality of units of data, and a controller coupled with the memory cells and which operates as follows; in response to the occurrence of at least one predefined condition, data are read from at least one unit of a first group of memory cells, it is then determined whether there are any errors in the read data, in response to at least errors being determined to exist in the read data, an effort is made to recover the data erroneously read from said at least one unit of the first group, if recovered, the recovered data are written into at least one unit of a second group of memory cells different from the first group of memory cells, and data read without errors from other units of the first group of memory cells are copied into units of the second group of memory cells other than its said at least one unit, thereby to consolidate in the second block data read without errors and recovered data originally of the first block. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22)
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23. A memory system, comprising:
groups of re-programmable non-volatile memory cells that store data as levels of charge therein, wherein individual ones of the groups store a plurality of units of data, and a controller coupled with the memory cells and which operates to; read data from at least a first group of memory cells, thereafter determine whether there are any errors in the data read from at least one unit of the first group of memory cells, in response to at least errors being determined to exist in the read data, an effort is made to recover the data erroneously read from said at least one unit of the first group, if recovered, the recovered data are written into at least one unit of a second group of memory cells different from the first group of memory cells, and data read without errors from other units of the first group of memory cells are copied into units of the second group of memory cells other than its said at least one unit, thereby to consolidate in the second block data read without errors and recovered data originally of the first block. - View Dependent Claims (24, 25, 26, 27, 28)
Specification
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Litigation Data
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Current AssigneeSanDisk Technologies LLC (Western Digital Corporation)
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Original AssigneeSanDisk Corporation (Western Digital Corporation)
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InventorsGonzalez, Carlos J., Conley, Kevin M.
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Primary Examiner(s)Elms, Richard T.
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Assistant Examiner(s)Luu, Pho M.
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Application NumberUS11/271,553Publication NumberTime in Patent Office565 DaysField of Search365/185.11, 365/185.33, 365/230.03US Class Current365/185.11CPC Class CodesG06F 11/106 Correcting systematically a...G06F 11/1068 in sector programmable memo...G11C 8/08 Word line control circuits,...
