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Clock-edge modulated serial link with DC-balance control

DC CAFC
  • US 7,627,044 B2
  • Filed: 10/31/2005
  • Issued: 12/01/2009
  • Est. Priority Date: 10/31/2005
  • Status: Active Grant
First Claim
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1. A signal transmitter, comprising:

  • a channel node to interface with a single direct current balanced differential channel; and

    circuitry connected to the channel node, the circuitry being configured to multiplex clock, data and control signals and apply them to the channel node, wherein the clock signal is pulse width modulated to incorporate direct current balancing control signals.

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