Partial block data programming and reading operations in a non-volatile memory
DC
First Claim
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1. A method of operating a non-volatile memory system, comprising:
- providing a plurality of blocks of memory storage elements that are individually erasable as a unit and which are individually organized into a plurality of pages of memory storage elements that are individually programmable together,programming at least one page of data in one of the plurality of blocks;
programming at least one page of new data in one of said one or another of the plurality of blocks, the at least one page of new data rendering the at least one page of data to become at least one page of superceded dataidentifying the at least one page of superceded data and the at least one page of new data by a common logical address,recording an indication of a relative time of programming the at least one page of new data and the at least one page of superceded data; and
wherein the at least one page of superceded data is less than all the data contained in said one block.
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Accused Products
Abstract
Data in less than all of the pages of a non-volatile memory block are updated by programming the new data in unused pages of either the same or another block. In order to prevent having to copy unchanged pages of data into the new block, or to program flags into superceded pages of data, the pages of new data are identified by the same logical address as the pages of data which they superceded and a time stamp is added to note when each page was written. When reading the data, the most recent pages of data are used and the older superceded pages of data are ignored. This technique is also applied to metablocks that include one block from each of several different units of a memory array, by directing all page updates to a single unused block in one of the units.
84 Citations
16 Claims
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1. A method of operating a non-volatile memory system, comprising:
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providing a plurality of blocks of memory storage elements that are individually erasable as a unit and which are individually organized into a plurality of pages of memory storage elements that are individually programmable together, programming at least one page of data in one of the plurality of blocks; programming at least one page of new data in one of said one or another of the plurality of blocks, the at least one page of new data rendering the at least one page of data to become at least one page of superceded data identifying the at least one page of superceded data and the at least one page of new data by a common logical address, recording an indication of a relative time of programming the at least one page of new data and the at least one page of superceded data; and wherein the at least one page of superceded data is less than all the data contained in said one block. - View Dependent Claims (2, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, 15, 16)
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3. A method of operating a non-volatile memory system, comprising:
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providing a plurality of blocks of memory storage elements that are individually erasable as a unit and which are individually organized into a plurality of pages of memory storage elements that are individually programmable together, programming at least one page of data in one of the plurality of blocks; programming at least one page of new data in one of said one or another of the plurality of blocks, the at least one page of new data rendering the at least one page of data to become at least one page of superceded data, identifying the at least one page of superceded data and the at least one page of new data by a common logical address, recording an indication of a relative time of programming the at least one page of new data and the at least one page of superceded data; and wherein the data in at least another page of said one block that is not replaced are not copied into said one or another block as part of substituting the new data for the superceded data.
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12. A method of operating a non-volatile memory system, comprising:
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providing a plurality of blocks of memory storage elements that are individually erasable as a unit and which are individually organized into a plurality of pages of memory storage elements that are individually programmable together, programming at least one page of data in one of the plurality of blocks; programming at least one page of new data in one of said one or another of the plurality of blocks, the at least one page of new data rendering the at least one page of data to become at least one page of superceded data, wherein pages within the individual blocks are programmed in a designated order, identifying the at least one page of superceded data and the at least one page of new data by a common logical address, reading pages of data within said one and, if new data has been programmed thereinto, another block in a reverse order from which they were programmed, and passing over any pages of data so read which have the same logical page address as a page whose data has already been read; and wherein the at least one page of superceded data is less than all the data contained in said one block.
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Specification
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Litigation Data
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Current AssigneeSanDisk Technologies LLC (Western Digital Corporation)
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Original AssigneeSanDisk Corporation (Western Digital Corporation)
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InventorsConley, Kevin M.
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Primary Examiner(s)Thai, Tuan V
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Assistant Examiner(s)Dinh, Ngoc V
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Application NumberUS12/900,397Publication NumberTime in Patent Office264 DaysField of Search711/103US Class Current711/103CPC Class CodesG06F 12/0246 in block erasable memory, e...G06F 2212/1016 Performance improvementG06F 2212/1032 Reliability improvement, da...G06F 2212/7202 Allocation control and poli...G06F 2212/7208 Multiple device management,...G06F 2212/7209 Validity control, e.g. usin...G11C 16/102 External programming circui...G11C 16/105 Circuits or methods for upd...G11C 2216/16 Flash programming of all th...
