Systems and methods for minimizing static leakage of an integrated circuit
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First Claim
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1. An adaptive leakage controller for adequately minimizing a static leakage of an integrated circuit, comprising:
- a capacitor configured to be charged to a positive supply voltage;
a transistor configured to discharge the capacitor at a rate in proportion to the static leakage; and
a control circuit configured to determine whether to adjust a negative voltage applied to a sleep transistor configured to control the static leakage based on a minimum rate of discharge of the capacitor.
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Abstract
A leakage manager system for adequately minimizing static leakage of an integrated circuit is disclosed. The leakage manager system includes a generator configured to generate a control signal to be applied to a sleep transistor. A monitor is configured to determine whether to adjust the control signal to adequately minimize the static leakage. In some embodiments, the monitor includes an emulated sleep transistor. A regulator is configured to adjust the control signal depending on the determination.
64 Citations
27 Claims
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1. An adaptive leakage controller for adequately minimizing a static leakage of an integrated circuit, comprising:
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a capacitor configured to be charged to a positive supply voltage; a transistor configured to discharge the capacitor at a rate in proportion to the static leakage; and a control circuit configured to determine whether to adjust a negative voltage applied to a sleep transistor configured to control the static leakage based on a minimum rate of discharge of the capacitor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A method of adequately minimizing static leakage of an integrated circuit comprising:
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charging a capacitor to a positive supply voltage; discharging the capacitor at a rate in proportion to the static leakage; and adjusting a negative voltage applied to a gate of a sleep transistor to adequately minimize the rate of discharge of the capacitor. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
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27. An integrated circuit comprising:
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two power supply terminals configured to power the integrated circuit, said power supply terminals including a Vdd positive supply terminal and a VSS ground terminal together defining a range of logic levels; logic components in series with a sleep transistor electrically connected to one of said power supply terminals, each of said logic components being a either a logic gate or a storage cell; a voltage generator configured to generate a voltage outside said range of logic levels; voltage generator control circuitry operably coupled to said voltage generator; circuitry configured to apply said voltage outside the range of logic levels to said sleep transistor during a power down mode; and a voltage regulator operably coupled to said voltage generator control circuitry.
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Specification
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Litigation Data
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Current AssigneeMosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
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Original AssigneeMosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
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InventorsSchwake, Steven J., Caplan, Randy J.
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Primary Examiner(s)ZWEIZIG, JEFFERY SHAWN
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Application NumberUS12/620,749Publication NumberTime in Patent Office608 DaysField of Search327/534, 327/535, 327/536, 327/537, 327/544US Class Current327/544CPC Class CodesH03K 19/0013 in field effect transistor ...H03K 19/0016 by using a control or a clo...
