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Low leakage and data retention circuitry

DC
  • US 8,253,438 B2
  • Filed: 03/29/2011
  • Issued: 08/28/2012
  • Est. Priority Date: 02/19/2004
  • Status: Active Grant
First Claim
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1. An integrated circuit comprising:

  • a plurality of power islands having associated power consumptions, each of the power islands including circuitries and sleep transistors in coupled relation with the circuitries, and the sleep transistors being included within the integrated circuit to facilitate reduction of power consumed by the circuitries;

    a power island manager configured to dynamically change the power consumptions based on needs and operation of the integrated circuit, the power island manager in communication with at least one of the power islands; and

    an adaptive leakage controller configured to control change of a variable voltage to be applied to the sleep transistors, and the power island manager configured to generate the variable voltage based on a control signal received from the adaptive leakage controller.

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