Partial block data programming and reading operations in a non-volatile memory
DC
First Claim
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1. A re-programmable non-volatile memory system, comprising:
- an array of storage elements organized into a plurality of blocks, each block having storage elements that are erasable together and organized into a plurality of pages, each page having storage elements that are accessed together and each page is programmable in a preset order in a block at a specified offset position,a memory controller for controlling the operations of the non-volatile memory system, the operations including;
(a) in response to a host command for programming and one or more pages of original user data addressable by logical addresses and received from the host, programming the one or more pages of original user data into a first one or more pages of storage elements in the preset order in at least a first one of the blocks,(b) in response to a host command for updating and one or more pages of updated user data received from the host, programming the received one or more pages of updated user data into a second one or more pages of storage elements in the preset order in at least a second one of the blocks without necessarily in the same offset positions as in the at least a first one of the blocks, and(c) in response to a host command for reading user data of specified logical addresses, reading at least the one or more pages of updated data from the at least the second one of the blocks with some of the specified logical addresses in common with that of original user data and reading pages of original user data that have not been updated from the at least the first one of the blocks with others of the specified logical addresses are associated.
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Accused Products
Abstract
Data in less than all of the pages of a non-volatile memory block are updated by programming the new data in unused pages of either the same or another block. In order to prevent having to copy unchanged pages of data into the new block, or to program flags into superceded pages of data, the pages of new data are identified by the same logical address as the pages of data which they superceded and a time stamp is added to note when each page was written. When reading the data, the most recent pages of data are used and the older superceded pages of data are ignored. This technique is also applied to metablocks that include one block from each of several different units of a memory array, by directing all page updates to a single unused block in one of the units.
74 Citations
15 Claims
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1. A re-programmable non-volatile memory system, comprising:
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an array of storage elements organized into a plurality of blocks, each block having storage elements that are erasable together and organized into a plurality of pages, each page having storage elements that are accessed together and each page is programmable in a preset order in a block at a specified offset position, a memory controller for controlling the operations of the non-volatile memory system, the operations including; (a) in response to a host command for programming and one or more pages of original user data addressable by logical addresses and received from the host, programming the one or more pages of original user data into a first one or more pages of storage elements in the preset order in at least a first one of the blocks, (b) in response to a host command for updating and one or more pages of updated user data received from the host, programming the received one or more pages of updated user data into a second one or more pages of storage elements in the preset order in at least a second one of the blocks without necessarily in the same offset positions as in the at least a first one of the blocks, and (c) in response to a host command for reading user data of specified logical addresses, reading at least the one or more pages of updated data from the at least the second one of the blocks with some of the specified logical addresses in common with that of original user data and reading pages of original user data that have not been updated from the at least the first one of the blocks with others of the specified logical addresses are associated. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. In a re-programmable non-volatile semiconductor memory system having an array of storage elements organized into a plurality of blocks, each block having storage elements that are erasable together and organized into a plurality of pages, each page having storage elements that are accessed together and each page is programmable in a preset order in a block at a specified offset position, a method of operating the memory system, comprising:
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programming original data into individual ones of a first plurality of pages in at least a first block, the original data having logical addresses associated therewith, thereafter programming an updated version of the original data into individual ones of a second plurality of pages in a second block, the updated version having logical addresses associated therewith and being less than the given number of pages of the original data programmed into the first plurality of pages, wherein the logical addresses associated with the updated version of the original data are the same as the logical addresses associated with the original data, wherein programming the second plurality of pages additionally comprises programming the updated version of the original data in those of the second plurality of pages that have different offset positions within the second block than the offset positions of the first plurality of pages within said at least the first block that contain original data with the same associated logical addresses, maintaining updatable address information that links physical addresses of the first and second blocks storing original and updated data with the logical addresses associated with the stored data, wherein the address information includes physical addresses of multiple blocks for individual logical addresses of original data having updated versions thereof, and thereafter reading data from the first and second plurality of pages by a process that includes accessing the updatable address information. - View Dependent Claims (11, 12, 13, 14, 15)
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Specification
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Litigation Data
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Current AssigneeSanDisk Technologies LLC (Western Digital Corporation)
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Original AssigneeSanDisk Corporation (Western Digital Corporation)
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InventorsConley, Kevin M.
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Primary Examiner(s)Thai, Tuan
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Assistant Examiner(s)DINH, NGOC V
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Application NumberUS13/168,756Publication NumberTime in Patent Office515 DaysField of Search711/103US Class Current711/103CPC Class CodesG06F 12/0246 in block erasable memory, e...G06F 2212/1016 Performance improvementG06F 2212/1032 Reliability improvement, da...G06F 2212/7202 Allocation control and poli...G06F 2212/7208 Multiple device management,...G06F 2212/7209 Validity control, e.g. usin...G11C 16/102 External programming circui...G11C 16/105 Circuits or methods for upd...G11C 2216/16 Flash programming of all th...
