Electronic system and method for selectively allowing access to a shared memory
DC
First Claim
1. A computing device, comprising:
- a central processing unit (CPU);
core logic coupled by a first bus to the CPU, the core logic having a first memory interface coupleable to a shared main memory;
a cache memory coupled to the CPU by the first bus;
a decoder/encoder coupleable to the shared main memory via a second memory interface;
an arbiter configured to receive shared memory access requests from the CPU and the decoder/encoder, the arbiter configured to arbitrate access to the shared main memory; and
a memory bus coupled to the first memory interface and the second memory interface, the memory bus configured to pass first data in real time between the shared main memory and the CPU via the first memory interface, the memory bus configured to pass second data in real time between the shared main memory and the decoder/encoder.
3 Assignments
Litigations
1 Petition
Accused Products
Abstract
An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory based on priority. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.
45 Citations
17 Claims
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1. A computing device, comprising:
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a central processing unit (CPU); core logic coupled by a first bus to the CPU, the core logic having a first memory interface coupleable to a shared main memory; a cache memory coupled to the CPU by the first bus; a decoder/encoder coupleable to the shared main memory via a second memory interface; an arbiter configured to receive shared memory access requests from the CPU and the decoder/encoder, the arbiter configured to arbitrate access to the shared main memory; and a memory bus coupled to the first memory interface and the second memory interface, the memory bus configured to pass first data in real time between the shared main memory and the CPU via the first memory interface, the memory bus configured to pass second data in real time between the shared main memory and the decoder/encoder. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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Specification
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- Resources
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Current AssigneeParthenon Unified Memory Architecture LLC (Acacia Research Corporation)
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Original AssigneeSTMicroelectronics Incorporated (STMicroelectronics NV)
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InventorsOwen, Jefferson Eugene, Diaz, Raul Zegers, Colavin, Osvaldo
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Primary Examiner(s)Nguyen, Hau
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Application NumberUS13/655,152Publication NumberTime in Patent Office523 DaysField of Search345/541, 345/535, 345/542, 345/547, 345/555US Class Current345/535CPC Class CodesG06F 13/1605 based on arbitration arbitr...G06F 13/18 based on priority control G...G06F 15/167 using a common memory, e.g....G06T 1/60 Memory managementG09G 2340/02 Handling of images in compr...G09G 2360/18 Use of a frame buffer in a ...G09G 5/001 Arbitration of resources in...G09G 5/363 Graphics controllersH04N 19/423 characterised by memory arr...H04N 19/427 Display on the fly, e.g. si...H04N 19/61 in combination with predict...H04N 21/443 OS processes, e.g. booting ...H04N 21/4435 Memory management allocatio...
