Three dimensional structure memory

US 8,824,159 B2
Filed: 03/31/2009
Issued: 09/02/2014
Est. Priority Date: 04/04/1997
Status: Expired due to Fees

First Claim

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1. An integrated circuit structure comprising:

a first substrate of semiconductor material with at least one of interconnections supported thereby and integrated circuitry formed thereon; and

a second substrate of semiconductor material made from a semiconductor wafer, wherein the second substrate is of one piece and is a thinned substantially flexible substrate with circuitry comprising a plurality of integrated circuit devices formed thereon, the plurality of integrated circuit devices defining an integrated circuit die having an area, a layer formed over the second substrate being bonded to a layer formed over the first substrate with conductive paths therebetween;

wherein the second substrate extends throughout at least a substantial portion of the area of the integrated circuit die.

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Abstract

A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

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24 Claims

1. An integrated circuit structure comprising:
- a first substrate of semiconductor material with at least one of interconnections supported thereby and integrated circuitry formed thereon; and
  
  a second substrate of semiconductor material made from a semiconductor wafer, wherein the second substrate is of one piece and is a thinned substantially flexible substrate with circuitry comprising a plurality of integrated circuit devices formed thereon, the plurality of integrated circuit devices defining an integrated circuit die having an area, a layer formed over the second substrate being bonded to a layer formed over the first substrate with conductive paths therebetween;
  
  wherein the second substrate extends throughout at least a substantial portion of the area of the integrated circuit die.
- View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
- - 2. The integrated circuit structure of claim 1, wherein the second substrate has a thickness of 50 microns or less.
  - 3. The integrated circuit structure of claim 1, wherein the second substrate has a thickness of 10 microns or less.
  - 4. The integrated circuit structure of claim 1, wherein the second substrate has a thickness between 1 and 8 microns.
  - 5. The integrated circuit structure of claim 1, wherein the second substrate has formed thereon a dielectric layer with a stress of 5×
    - 10⁸dynes/cm²tensile or less, wherein the dielectric layer is at least one of silicon dioxide and an oxide of silicon.
  - 6. The integrated circuit structure of claim 1, wherein the circuitry of the second substrate is one of logic circuitry and memory circuitry.
  - 7. The integrated circuit structure of claim 1, wherein at least two of:
    - the second substrate has a thickness of 50 microns or less;
      
      the first substrate is a non-semiconductor material;
      
      the second substrate has formed thereon a dielectric layer with a stress of 5×
      
      10⁸dynes/cm²tensile or less;
      
      the dielectric is at least one of silicon dioxide and an oxide of silicon;
      
      the circuitry of the second substrate is one of logic circuitry and memory circuitry;
      
      at least one vertical conductive path passes through at least one of the first substrate and the second substrate and is insulated from the at least one of the first and second substrate by a non-conductive material having a stress of 5×
      
      10⁸dynes/cm²tensile or less;
      
      the layer formed over the first substrate and the layer formed over the second substrate comprise bond surfaces and bonded areas, wherein the bonded areas comprise a majority of the bond surfaces.
  - 8. The integrated circuit structure of claim 1, wherein at least three of:
    - the second substrate has a thickness of 50 microns or less;
      
      the first substrate is a non-semiconductor material;
      
      the second substrate has formed thereon a dielectric layer with a stress of 5×
      
      10⁸dynes/cm²tensile or less;
      
      the dielectric is at least one of silicon dioxide and an oxide of silicon;
      
      the circuitry of the second substrate is one of logic circuitry and memory circuitry;
      
      at least one vertical conductive path passes through at least one of the first substrate and the second substrate and is insulated from the at least one of the first and second substrate by a non-conductive material having a stress of 5×
      
      10⁸dynes/cm²tensile or less;
      
      the layer formed over the first substrate and the layer formed over the second substrate comprise bond surfaces and bonded areas, wherein the bonded areas comprise a majority of the bond surfaces.
  - 9. The integrated circuit structure of claim 1, wherein at least four of:
    - the second substrate has a thickness of 50 microns or less;
      
      the first substrate is a non-semiconductor material;
      
      the second substrate has formed thereon a dielectric layer with a stress of 5×
      
      10⁸dynes/cm²tensile or less;
      
      the dielectric is at least one of silicon dioxide and an oxide of silicon;
      
      the circuitry of the second substrate is one of logic circuitry and memory circuitry;
      
      at least one vertical conductive path passes through at least one of the first substrate and the second substrate and is insulated from the at least one of the first and second substrate by a non-conductive material having a stress of 5×
      
      10⁸dynes/cm²tensile or less;
      
      the layers formed over the first and second substrates comprise bond surfaces and bonded areas, wherein the bonded areas comprise a majority of the bond surfaces.
  - 10. The integrated circuit structure of claim 1, comprising at least one vertical conductive path passing through at least one of the first substrate and the second substrate and insulated from the at least one of the first and second substrate by a non-conductive material having a stress of 5×
    - 10⁸dynes/cm²tensile or less.
  - 11. The integrated circuit structure of claim 1, wherein the layer formed over the first substrate and the layer formed over the second substrate comprise bond surfaces and bonded areas of the bond surfaces, wherein the bonded areas comprise a majority of the bond surfaces.
  - 12. The integrated circuit structure of claim 10, wherein the nonconductive material is at least one of silicon dioxide, silicon nitride, an oxide of silicon, and a nitride of silicon.
  - 13. The integrated circuit structure of claim 7, comprising at least one vertical conductive path passing through at least one of the first substrate and the second substrate and insulated from the at least one of the first and second substrate by a non-conductive material having a stress of 5×
    - 10⁸dynes/cm²tensile or less.
  - 14. The integrated circuit structure of claim 7, wherein the nonconductive material is at least one of silicon dioxide, silicon nitride, an oxide of silicon, and a nitride of silicon.
  - 15. The integrated circuit structure of claim 8, wherein the nonconductive material is at least one of silicon dioxide, silicon nitride, an oxide of silicon, and a nitride of silicon.
  - 16. The integrated circuit structure of claim 9, wherein the nonconductive material is at least one of silicon dioxide, silicon nitride, an oxide of silicon, and a nitride of silicon.
  - 17. The integrated circuit structure of claim 13, wherein the nonconductive material is at least one of silicon dioxide, silicon nitride, an oxide of silicon, and a nitride of silicon.
  - 18. The integrated circuit structure of claim 13, wherein the vertical conductive path comprises a metal conductor.
  - 19. The integrated circuit structure of claim 7, wherein the vertical conductive path comprises a metal conductor.
  - 20. The integrated circuit structure of claim 8, wherein the vertical conductive path comprises a metal conductor.
  - 21. The integrated circuit structure of claim 9, wherein the vertical conductive path comprises a metal conductor.
  - 22. The integrated circuit structure of claim 10, wherein the vertical conductive path comprises a metal conductor.
  - 23. The integrated circuit structure of claim 1, further comprising:
    - a third substrate made from a semiconductor wafer, a layer formed over the third substrate being bonded to a further layer formed over the first substrate to form conductive paths therebetween, wherein the third substrate is a thinned substantially flexible substrate with a plurality of integrated circuit devices formed thereon;
      
      wherein the second substrate comprises circuitry of a type fabricated using a first semiconductor process, and the third substrate comprises circuitry of a type fabricated using a second different semiconductor process.
  - 24. The integrated circuit structure of claim 7, further comprising:
    - a third substrate made from a semiconductor wafer, a layer formed over the third substrate being bonded to a further layer formed over the first substrate to form conductive paths therebetween, wherein the third substrate is a thinned substantially flexible substrate with a plurality of integrated circuit devices formed thereon;
      
      wherein the second substrate comprises circuitry of a type fabricated using a first semiconductor process, and the third substrate comprises circuitry of a type fabricated using a second different semiconductor process.

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Current Assignee
Elm 3DS Innovations LLC
Original Assignee
Elm 3DS Innovations LLC
Inventors
Leedy, Glenn J.
Primary Examiner(s)
Chen, Xiaoliang

Application Number

US12/414,749
Publication Number

US 20090230501A1
Time in Patent Office

1,981 Days
Field of Search

361/760, 361/717, 361/719, 361/744, 361/790, 361/792, 174/255, 174/257, 257/48, 257/712, 257/668
US Class Current

361/760
CPC Class Codes

G11C 5/02   Disposition of storage elem...

G11C 5/06   Arrangements for interconne...

H01L 21/76898   formed through a semiconduc...

H01L 2224/8083   Solid-solid interdiffusion

H01L 2224/8384   Sintering

H01L 23/481   Internal lead connections, ...

H01L 23/5226   Via connections in a multil...

H01L 25/0657   Stacked arrangements of dev...

H01L 27/0688   Integrated circuits having ...

H01L 29/02   Semiconductor bodies ; Mult...

H01L 2924/01079   Gold [Au]

H10B 12/50   Peripheral circuit region s...

Y10S 438/977   Thinning or removal of subs...

Three dimensional structure memory

First Claim

4 Assignments

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Accused Products

Abstract

384 Citations

24 Claims

Specification

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Three dimensional structure memory

First Claim

4 Assignments

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Subscription Required

0 Petitions

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Accused Products

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Abstract

384 Citations

24 Claims

Specification

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Solutions

Use Cases

Quick Links