Method and apparatus for managing the flow of data within a switching device
DCFirst Claim
1. A switching device comprising:
- a master control process including a memory to store routing information; and
a first interface card in communication with the master control process, the first interface card comprising (i) a first local memory including a plurality of entries that collectively contain a portion of the routing information stored in the memory of the master control process and (ii) a first controller to update contents of at least one entry of the first local memory from the memory of the master control process in response to an event.
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Abstract
A method and apparatus for managing the flow of data within a switching device is provided. The switching device includes network interface cards connected to a common backplane. Each interface card is configured to support the maximum transfer rate of the backplane by maintaining a “pending” queue to track data that has been received but for which the appropriate routing destination has not yet been determined. The switching device includes a switch controller that maintains a central card/port-to-address table. When an interface card receives data with a destination address that is not known to the interface card, the interface card performs a direct memory access over a bus that is separate from the backplane to read routing data directly from the central table in the switch controller. Each interface card builds and maintains a routing information table in its own local memory that only includes a routing information for the destination addresses that the interface card is most likely to receive.
26 Citations
69 Claims
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1. A switching device comprising:
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a master control process including a memory to store routing information; and
a first interface card in communication with the master control process, the first interface card comprising (i) a first local memory including a plurality of entries that collectively contain a portion of the routing information stored in the memory of the master control process and (ii) a first controller to update contents of at least one entry of the first local memory from the memory of the master control process in response to an event. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A switching device comprising:
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a backplane;
a bus;
a master control process coupled to the backplane and the bus, the master control process including a memory to store routing information; and
a first interface card coupled to the backplane and the bus, the first interface card comprising (i) a first local memory including a plurality of entries that collectively contain a portion of the routing information stored in the memory of the master control process and (ii) a first controller to receive the portion of the routing information from the memory of the master control process via the bus upon receiving data that includes a destination address about which no routing information is currently stored in the first local memory. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47)
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48. The switching device comprising:
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a backplane;
a bus;
a master control process coupled to the backplane and the bus, the master control process including a memory to the store routing information; and
a plurality of interface cards coupled to the backplane and the bus, each of the plurality of interface cards including a local memory to store a table featuring a portion of the routing information and a memory controller to receive particular routing information from the memory of the master control process upon receiving a cell that includes a destination address about which the particular routing information is currently not stored. - View Dependent Claims (49)
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50. The switching device of claim 48, wherein the portion of the routing information is a subset of the routing information storing in the memory of the master control process.
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51. The switching device of claim 48, wherein the bus is a multiple line bus that interconnects the memory controllers of the plurality of interface cards.
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52. The switching device of claim 48, wherein the master control process resides on one of the plurality of interface cards.
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53. The switching device of claim 48, wherein an address space of the memory of the master control process is non-overlapping with address spaces of each of the local memories of the plurality of interface cards.
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54. The switching device of claim 53, wherein the address spaces of each of the local memories of the plurality of interface cards are non-overlapping with each other.
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55. The switching device of claim 48, wherein direct memory accesses by the memory controllers of the plurality of interface cards are performed over the bus.
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56. The switching device of claim 48, wherein the local memory of at least one of the plurality of interface cards contains the portion of the routing information by reading the portion of the routing information from the memory of the master control process.
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57. The switching device of claim 48 wherein the local memory of at least one of the plurality of interface cards contains the portion of the routing information by the master control process writing the portion of the routing information to the local memory.
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58. The switching device of claim 48, wherein the cell is a packet including the destination address.
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59. The switching device of claim 49, wherein the cell is a packet including the destination address.
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60. The switching device of claim 50, wherein the cell is a packet including the destination address.
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61. The switching device of claim 51, wherein the cell is a packet including the destination address.
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62. The switching device of claim 52, wherein the cell is a packet including the destination address.
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63. The switching device of claim 53, wherein the cell is a packet including the destination address.
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64. The switching device of claim 54, wherein the cell is a packet including the destination address.
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65. The switching device of claim 55, wherein the cell is a packet including the destination address.
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66. The switching device of claim 56, wherein the cell is a packet including the destination address.
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67. The switching device of claim 57, wherein the cell is a packet including the destination address.
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68. The switching device of claim 48, wherein the bus couples the master control process to the memory controllers of the plurality of interface cards.
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69. The switching device of claim 48, wherein the memory controller performing a direct memory access operation on the memory of the master control process to receive the particular routing information.
Specification