Clock synchronous semiconductor memory device
First Claim
1. A semiconductor device comprising:
- a plurality of input buffers of different types from each other; and
program circuitry for generating a signal alternatively driving said plurality of input buffers to an operable state, said plurality of input buffers selectively set to an operable state according to an output signal of said program circuitry and driving an internal node according to a received signal when made active.
10 Assignments
0 Petitions
Accused Products
Abstract
In a control circuit and an address buffer circuit, buffer circuits of plural types are provided to each of pin terminals and an input buffer of one type is activated according a state control signal group. In a standby state, current paths of the control buffer circuit and the address buffer circuit are selectively cut off according to a CS cut mode instructing signal stored in a mode register and an internal chip select signal. Furthermore, when a low power consumption mode is specified, a current path of a CLK buffer for generating an internal clock signal is cut off according to an external clock enable signal and a low power mode instructing signal, and the current paths of the control buffer circuit and the address buffer circuit are also cut-off.
30 Citations
18 Claims
-
1. A semiconductor device comprising:
-
a plurality of input buffers of different types from each other; and
program circuitry for generating a signal alternatively driving said plurality of input buffers to an operable state, said plurality of input buffers selectively set to an operable state according to an output signal of said program circuitry and driving an internal node according to a received signal when made active. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
-
-
11. A semiconductor device comprising:
-
signal input circuitry including an input buffer for buffering a signal provided externally and generating an internal signal when active;
register circuitry for storing a signal specifying whether control on said signal input circuitry by an operation activation signal is valid, said operation activating signal indicating that an external signal is a valid signal; and
an activation control circuit for selectively activating said signal input circuitry according to said operation activating signal and the signal stored in said register circuit, said activation control circuit selectively activating said signal input circuitry according to said operation activating signal when the stored signal in said register circuit indicates that control on said signal input circuitry by said operation activating signal is valid, and setting said signal input circuitry to an operating state all the times when said stored signal in said register circuit indicates that control on said signal input circuit by said operation activating signal is valid. - View Dependent Claims (12, 13, 14, 16, 17, 18)
-
-
15. A semiconductor device comprising:
-
a buffer circuit for buffering a signal provided externally when active;
a clock buffer for generating an internal clock signal according to an external clock signal when a clock enable signal is active;
clock detection circuitry for detecting whether said clock enable signal is held inactive for a prescribed period of time in a low power operation mode; and
control circuitry for setting said buffer circuit and said clock buffer to an inactive state in response to a detection signal of said clock detection circuitry.
-
Specification