Three dimensional structure memory

US 20090174082A1
Filed: 03/17/2009
Published: 07/09/2009
Est. Priority Date: 04/04/1997
Status: Active Grant

First Claim

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1. A stacked integrated circuit comprising:

a circuit substrate;

a first integrated circuit having circuitry formed on a front surface thereof, the front surface being bonded to the circuit substrate; and

one or more additional integrated circuits each having circuitry formed on respective front surfaces thereof, each additional integrated circuit being bonded by the front surface thereof to a back surface of an adjacent integrated circuit.

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Abstract

A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

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29 Claims

1. A stacked integrated circuit comprising:
- a circuit substrate;
  
  a first integrated circuit having circuitry formed on a front surface thereof, the front surface being bonded to the circuit substrate; and
  
  one or more additional integrated circuits each having circuitry formed on respective front surfaces thereof, each additional integrated circuit being bonded by the front surface thereof to a back surface of an adjacent integrated circuit.
- View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29)
- - 2. The apparatus of claim 1, wherein the circuit substrate is an integrated circuit substrate having circuitry formed on a front surface thereof wherein the front surfaces of the integrated circuit substrate and the first integrated circuit are bonded together.
  - 3. The apparatus of claim 2, further comprising a thermal diffusion bond joining the integrated circuit substrate and the first integrated circuit.
  - 4. The apparatus of claim 2, further comprising thermal diffusion bonds joining each additional integrated circuit to an adjacent integrated circuit.
  - 5. The apparatus of claim 1, further comprising vertical interconnects connecting circuitry of the first integrated circuit and circuitry of the second integrated circuit, wherein a plurality of interconnects are closely arrayed to form a group of interconnects.
  - 6. The apparatus of claim 5, wherein a group of interconnects extends continuously between multiple integrated circuits.
  - 7. The apparatus of claim 5, wherein the interconnects are formed at least in part by a thermal diffusion bond.
  - 8. The apparatus of claim 1, wherein the first integrated circuit and the additional integrated circuit are formed with one of single crystal semiconductor material and polycrystalline semiconductor material.
  - 9. The apparatus of claim 1, wherein one of the first and additional integrated circuits are formed using a different process technology than another of the first and second integrated circuits, the different process technology being selected from a group consisting of DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance.
  - 10. The apparatus of claim 1, wherein at least one of the first and additional integrated circuits comprises a microprocessor.
  - 11. The apparatus of claim 1, further comprising at least one memory integrated circuit and at least one logic integrated circuit, wherein the at least one logic integrated circuit performs testing of the at least one memory integrated circuit.
  - 12. The apparatus of claim 1, further comprising at least one memory integrated circuit having multiple memory locations including at least one memory location used for sparing, wherein data from the at least one memory location on the at least one memory integrated circuit is used instead of data from a defective memory location on the at least one memory integrated circuit.
  - 13. The apparatus of claim 1, further comprising at least one memory integrated circuit and at least one logic integrated circuit, wherein the at least one logic integrated circuit performs programmable gate line address assignment with respect to the at least one memory integrated circuit.
  - 14. The apparatus of claim 1, wherein a plurality of interior vertical interconnections traverse at least one of the integrated circuits.
  - 15. The apparatus of claim 1, wherein continuous vertical interconnections connect circuitry of the first and second integrated circuits.
  - 16. The apparatus of claim 1, wherein information processing is performed on data routed between circuitry on the first and second integrated circuits.
  - 17. The apparatus of claim 1, wherein at least one integrated circuit has reconfiguration circuitry.
  - 18. The apparatus of claim 1, further comprising at least one logic integrated circuit having logic for performing at least one of the following functions:
    - virtual memory management, ECC, indirect addressing, content addressing, data compression, data decompression, graphics acceleration, audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, power management and database processing.
  - 19. The apparatus of claim 1, further comprising:
    - a memory array having a plurality of memory cells, a plurality of data lines, and a plurality of gate lines, each memory storage cell storing a data value and comprising circuitry for coupling that data value to one of said data lines in response to a gate control signal on one of said gate lines;
      
      circuitry for generating a gate control signal in response to an address, including means for mapping addresses to gate lines; and
      
      a controller for determining that one of said memory cells is defective and for altering said mapping to eliminate references to said one of said memory cells.
  - 20. The apparatus of claim 1, further comprising:
    - one or more controller integrated circuits;
      
      one or more memory integrated circuits;
      
      a plurality of data lines and a plurality of gate lines on each memory integrated circuit;
      
      an array of memory cells on each memory integrated circuit, each memory cell storing a data value and comprising circuitry for coupling that data value to one of said data lines in response to the selection of one of said gate lines;
      
      a gate line selection circuit for enabling a gate line for a memory operation, said gate line selection circuit comprising programmable gates to receive address assignments for one or more of said gate lines, said address assignments for determining which of said gate lines is selected for each programmed address assignment; and
      
      controller logic for determining that one of said array memory cells is defective and for altering in at least one instance said address assignments of said gate lines to eliminate references to that gate line that causes that defective memory cell to couple a data value to one of said data lines.
  - 21. The apparatus of claim 20, wherein said controller logic tests said memory cells periodically to determine if any of said memory cells is defective and wherein said controller eliminates references in said address assignments to gate lines that cause said detected defective memory cells to couple data values to said data lines.
  - 22. The apparatus of claim 20, further comprising programmable logic to prevent the use of data values from data lines when gate lines cause said detected defective memory cells to couple data values to said data lines.
  - 23. The apparatus of claim 20, wherein said memory cells are arranged within physical space in a physical order and are arranged within an address space in a logical order, wherein said physical order of at least one memory cell is different than the logical order of that memory cell.
  - 24. The apparatus of claim 20, wherein external testing of the controller logic together with testing by the controller logic of the memory cells achieves a functional testing of a preponderance of the memory cells.
  - 25. The apparatus of claim 20, wherein testing by the controller logic of the memory cells substantially reduces or eliminates the need for external testing of the memory cells of the one or more memory integrated circuits.
  - 26. The apparatus of claim 20 wherein altering said address assignments comprises preventing the use of at least one defective gate line and replacing references to memory cells addressed using said defective gate line with references to spare memory cells addressed using a spare gate line.
  - 27. The apparatus of claim 1, wherein the first integrated circuit is fabricated using one process technology, and the one or more additional integrated circuits are fabricated using a different process technology.
  - 28. The apparatus of claim 1, wherein at least one of the integrated circuits has a thickness of one of 10 microns or less and 50 microns or less.
  - 29. The apparatus of claim 1, wherein at least one of the integrated circuits is formed with a low stress dielectric, wherein the low stress dielectric is at least one of a silicon dioxide dielectric and an oxide of silicon dielectric and is caused to have a tensile stress of about 5×
    - 10⁸dynes/cm²or less.

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Current Assignee
Elm 3DS Innovations LLC
Original Assignee
Glenn J. Leedy
Inventors
Leedy, Glenn J

Granted Patent

US 8,629,542 B2
Time in Patent Office

Days
Field of Search
US Class Current

257/777
CPC Class Codes

G11C 5/02   Disposition of storage elem...

G11C 5/06   Arrangements for interconne...

H01L 21/76898   formed through a semiconduc...

H01L 2224/8083   Solid-solid interdiffusion

H01L 2224/8384   Sintering

H01L 23/481   Internal lead connections, ...

H01L 23/5226   Via connections in a multil...

H01L 25/0657   Stacked arrangements of dev...

H01L 27/0688   Integrated circuits having ...

H01L 29/02   Semiconductor bodies ; Mult...

H01L 2924/01079   Gold [Au]

H10B 12/50   Peripheral circuit region s...

Y10S 438/977   Thinning or removal of subs...

Three dimensional structure memory

First Claim

4 Assignments

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Abstract

173 Citations

29 Claims

Specification

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Three dimensional structure memory

First Claim

4 Assignments

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0 Petitions

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Accused Products

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Abstract

173 Citations

29 Claims

Specification

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Solutions

Use Cases

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