Three dimensional structure memory

US 20090230501A1
Filed: 03/31/2009
Published: 09/17/2009
Est. Priority Date: 04/04/1997
Status: Active Grant

First Claim

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1. An integrated circuit structure comprising:

a first substrate with at least one of interconnections and integrated circuitry formed thereon; and

a second substrate bonded to the first substrate to form conductive paths between the first substrate and the second substrate, wherein the second substrate is a thinned substantially flexible substrate with integrated circuitry formed thereon.

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Abstract

A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

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20 Claims

1. An integrated circuit structure comprising:
- a first substrate with at least one of interconnections and integrated circuitry formed thereon; and
  
  a second substrate bonded to the first substrate to form conductive paths between the first substrate and the second substrate, wherein the second substrate is a thinned substantially flexible substrate with integrated circuitry formed thereon.
- View Dependent Claims (2, 3, 4, 5, 6, 7, 18, 19, 20)
- - 2. The apparatus of claim 1, wherein the second substrate has a thickness of 50 microns or less.
  - 3. The apparatus of claim 1, wherein the second substrate has a thickness of 10 microns or less.
  - 4. The apparatus of claim 1, wherein the second substrate has a thickness between 1 and 8 microns.
  - 5. The apparatus of claim 1, wherein the first substrate is a non-semiconductor material.
  - 6. The apparatus of claim 1, wherein the second substrate is formed of tensile dielectric with a stress of about 5×
    - 10⁸dynes/cm2 or less, wherein the dielectric is at least one of silicon dioxide and an oxide of silicon.
  - 7. The apparatus of claim 1, wherein the circuitry of the second substrate is one of logic circuitry and memory circuitry.
  - 18. The apparatus of claim 1, wherein at least two of:
    - the second substrate has a thickness of 50 microns or less;
      
      the first substrate is a non-semiconductor material;
      
      the second substrate is formed of tensile dielectric with a stress of about 5×
      
      10⁸dynes/cm2 or less;
      
      the dielectric is at least one of silicon dioxide and an oxide of silicon;
      
      the circuitry of the second substrate is one of logic circuitry and memory circuitry.
  - 19. The apparatus of claim 1, wherein at least three of:
    - the second substrate has a thickness of 50 microns or less;
      
      the first substrate is a non-semiconductor material;
      
      the second substrate is formed of tensile dielectric with a stress of about 5×
      
      10⁸dynes/cm2 or less;
      
      the dielectric is at least one of silicon dioxide and an oxide of silicon;
      
      the circuitry of the second substrate is one of logic circuitry and memory circuitry.
  - 20. The apparatus of claim 1, wherein at least four of:
    - the second substrate has a thickness of 50 microns or less;
      
      the first substrate is a non-semiconductor material;
      
      the second substrate is formed of tensile dielectric with a stress of about 5×
      
      10⁸dynes/cm2 or less;
      
      the dielectric is at least one of silicon dioxide and an oxide of silicon;
      
      the circuitry of the second substrate is one of logic circuitry and memory circuitry.

8. An integrated circuit structure comprising:
- a first substrate with at least one of interconnections and integrated circuitry formed thereon; and
  
  a second substrate bonded to the first substrate with interconnections formed between the first substrate and the second substrate, wherein the second substrate is a thinned substantially flexible substrate with integrated circuitry formed thereon.
- View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16, 17)
- - 9. The apparatus of claim 8, wherein the second substrate has a thickness of 50 microns or less.
  - 10. The apparatus of claim 8, wherein the second substrate has a thickness of 10 microns or less.
  - 11. The apparatus of claim 8, wherein the second substrate has a thickness between 1 and 8 microns.
  - 12. The apparatus of claim 8, wherein the first substrate is a non-semiconductor material.
  - 13. The apparatus of claim 8, wherein the second substrate is formed of tensile dielectric with a stress of about 5×
    - 10⁸dynes/cm2 or less, wherein the dielectric is at least one of silicon dioxide and an oxide of silicon.
  - 14. The apparatus of claim 8, wherein the circuitry of the second substrate is one of logic circuitry and memory circuitry.
  - 15. The apparatus of claim 8, wherein at least two of:
    - the second substrate has a thickness of 50 microns or less;
      
      the first substrate is a non-semiconductor material;
      
      the second substrate is formed of tensile dielectric with a stress of about 5×
      
      10⁸dynes/cm2 or less;
      
      the dielectric is at least one of silicon dioxide and an oxide of silicon;
      
      the circuitry of the second substrate is one of logic circuitry and memory circuitry.
  - 16. The apparatus of claim 8, wherein at least three of:
    - the second substrate has a thickness of 50 microns or less;
      
      the first substrate is a non-semiconductor material;
      
      the second substrate is formed of tensile dielectric with a stress of about 5×
      
      10⁸dynes/cm2 or less;
      
      the dielectric is at least one of silicon dioxide and an oxide of silicon;
      
      the circuitry of the second substrate is one of logic circuitry and memory circuitry.
  - 17. The apparatus of claim 8, wherein at least four of:
    - the second substrate has a thickness of 50 microns or less;
      
      the first substrate is a non-semiconductor material;
      
      the second substrate is formed of tensile dielectric with a stress of about 5×
      
      10⁸dynes/cm2 or less;
      
      the dielectric is at least one of silicon dioxide and an oxide of silicon;
      
      the circuitry of the second substrate is one of logic circuitry and memory circuitry.

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Current Assignee
Elm 3DS Innovations LLC
Original Assignee
Elm 3DS Innovations LLC
Inventors
Leedy, Glenn J.

Granted Patent

US 8,824,159 B2
Time in Patent Office

Days
Field of Search
US Class Current

257/499
CPC Class Codes

G11C 5/02   Disposition of storage elem...

G11C 5/06   Arrangements for interconne...

H01L 21/76898   formed through a semiconduc...

H01L 2224/8083   Solid-solid interdiffusion

H01L 2224/8384   Sintering

H01L 23/481   Internal lead connections, ...

H01L 23/5226   Via connections in a multil...

H01L 25/0657   Stacked arrangements of dev...

H01L 27/0688   Integrated circuits having ...

H01L 29/02   Semiconductor bodies ; Mult...

H01L 2924/01079   Gold [Au]

H10B 12/50   Peripheral circuit region s...

Y10S 438/977   Thinning or removal of subs...

Three dimensional structure memory

First Claim

4 Assignments

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Accused Products

Abstract

172 Citations

20 Claims

Specification

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Three dimensional structure memory

First Claim

4 Assignments

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Subscription Required

0 Petitions

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Accused Products

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Abstract

172 Citations

20 Claims

Specification

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Solutions

Use Cases

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