SYSTEMS AND METHODS FOR MINIMIZING STATIC LEAKAGE OF AN INTEGRATED CIRCUIT

US 20100066439A1
Filed: 11/18/2009
Published: 03/18/2010
Est. Priority Date: 07/09/2004
Status: Active Grant

First Claim

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1. An adaptive leakage controller for adequately minimizing a static leakage of an integrated circuit, comprising:

a capacitor configured to be charged to a positive supply voltage;

a transistor configured to discharge the capacitor at a rate in proportion to the static leakage; and

a control circuit configured to determine whether to adjust a negative voltage applied to a sleep transistor configured to control the static leakage based on a minimum rate of discharge of the capacitor.

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Abstract

A leakage manager system for adequately minimizing static leakage of an integrated circuit is disclosed. The leakage manager system includes a generator configured to generate a control signal to be applied to a sleep transistor. A monitor is configured to determine whether to adjust the control signal to adequately minimize the static leakage. In some embodiments, the monitor includes an emulated sleep transistor. A regulator is configured to adjust the control signal depending on the determination.

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27 Claims

1. An adaptive leakage controller for adequately minimizing a static leakage of an integrated circuit, comprising:
- a capacitor configured to be charged to a positive supply voltage;
  
  a transistor configured to discharge the capacitor at a rate in proportion to the static leakage; and
  
  a control circuit configured to determine whether to adjust a negative voltage applied to a sleep transistor configured to control the static leakage based on a minimum rate of discharge of the capacitor.
- View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
- - 2. The adaptive leakage controller of claim 1 wherein the control circuit comprises:
    - a variable reference voltage; and
      
      a measuring circuit configured to measure a time required to discharge the capacitor to a level substantially equal to the variable reference voltage.
  - 3. The adaptive leakage controller of claim 2 wherein the measuring circuit comprises a counter.
  - 4. The adaptive leakage controller of claim 3 further comprising:
    - a register operably coupled to the counter.
  - 5. The adaptive leakage controller of claim 4 further comprising:
    - a state logic machine operably coupled to the register.
  - 6. The adaptive leakage controller of claim 1 further comprising:
    - another transistor operably coupled to the capacitor and configured to charge the capacitor to a positive power supply.
  - 7. The adaptive leakage controller of claim 1 wherein the control circuit is configured to periodically determine whether to adjust the negative voltage.
  - 8. The adaptive leakage controller of claim 1 wherein the control circuit is configured to continuously determine whether to adjust the negative voltage.
  - 9. The adaptive leakage controller of claim 1 wherein the control circuit is configured to generate a digital control signal based on the negative voltage.
  - 10. The adaptive leakage controller of claim 1 wherein the negative voltage is generated within the integrated circuit.
  - 11. The adaptive leakage controller of claim 1 in combination with a charge pump configured to generate the negative voltage.
  - 12. The adaptive leakage controller of claim 1 in combination with a negative voltage regulator configured to adjust the negative voltage.
  - 13. The adaptive leakage controller and negative voltage regulator of claim 12, wherein the negative voltage regulator is configured to generate a signal that enables a change in the magnitude of the negative voltage.
  - 14. The adaptive leakage controller of claim 1, wherein the adaptive leakage controller is integrated into the integrated circuit.

15. A method of adequately minimizing static leakage of an integrated circuit comprising:
- charging a capacitor to a positive supply voltage;
  
  discharging the capacitor at a rate in proportion to the static leakage; and
  
  adjusting a negative voltage applied to a gate of a sleep transistor to adequately minimize the rate of discharge of the capacitor.
- View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
- - 16. The method of claim 15, wherein adjusting the negative voltage includes generating a digital control signal.
  - 17. The method of claim 15, further comprising measuring a time to discharge the capacitor to a predetermined value.
  - 18. The method of claim 15, further comprising:
    - measuring a first time required to discharge the capacitor to a first predetermined value;
      
      measuring a second time required to discharge the capacitor to a second predetermined value; and
      
      adjusting the negative voltage depending on a comparison between the first and second times.
  - 19. The method of claim 18 further comprising:
    - charging the capacitor between measuring the first and second times required to discharge the capacitor.
  - 20. The method of claim 18 wherein measuring the first and second times includes storing first and second counts that correspond to the first and second times, respectively.
  - 21. The method of claim 20 wherein the comparison is a comparison of the first and second counts.
  - 22. The method of claim 21 wherein adjusting the negative voltage depending on the comparison includes incrementing a digital control signal if the first count is smaller than the second count.
  - 23. The method of claim 22 wherein adjusting the negative voltage depending on the comparison includes reverting to a prior value for a digital control signal if the first count is greater than the second count.
  - 24. The method of claim 15 wherein adjusting the negative voltage occurs periodically.
  - 25. The method of claim 15 wherein adjusting the negative voltage occurs continuously.
  - 26. The method of claim 15 further comprising:
    - generating the negative voltage within the integrated circuit.

27. An integrated circuit comprising:
- two power supply terminals configured to power the integrated circuit, said power supply terminals including a V_dd'"'"' positive supply terminal and a V_SSground terminal together defining a range of logic levels;
  
  logic components in series with a sleep transistor electrically connected to one of said power supply terminals, each of said logic components being a either a logic gate or a storage cell;
  
  a voltage generator configured to generate a voltage outside said range of logic levels;
  
  voltage generator control circuitry operably coupled to said voltage generator;
  
  circuitry configured to apply said voltage outside the range of logic levels to said sleep transistor during a power down mode; and
  
  a voltage regulator operably coupled to said voltage generator control circuitry.

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Current Assignee
Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
Original Assignee
Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
Inventors
Caplan, Randy J., Schwake, Steven J.

Granted Patent

US 7,982,532 B2
Time in Patent Office

Days
Field of Search
US Class Current

327/535
CPC Class Codes

H03K 19/0013 in field effect transistor ...

H03K 19/0016 by using a control or a clo...

SYSTEMS AND METHODS FOR MINIMIZING STATIC LEAKAGE OF AN INTEGRATED CIRCUIT

First Claim

11 Assignments

0 Petitions

Accused Products

Abstract

59 Citations

27 Claims

Specification

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SYSTEMS AND METHODS FOR MINIMIZING STATIC LEAKAGE OF AN INTEGRATED CIRCUIT

First Claim

11 Assignments

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Subscription Required

0 Petitions

Subscription Required

Accused Products

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Abstract

59 Citations

27 Claims

Specification

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Solutions

Use Cases

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