Low Leakage and Data Retention Circuitry
14 Assignments
0 Petitions
Accused Products
Abstract
An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.
11 Citations
82 Claims
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1-63. -63. (canceled)
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64. An integrated circuit comprising:
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a plurality of power islands having associated power consumptions, each of the power islands including circuitries and sleep transistors in coupled relation with the circuitries, and the sleep transistors being included within the integrated circuit to facilitate reduction of power consumed by the circuitries; a power island manager configured to dynamically change the power consumptions based on needs and operation of the integrated circuit, the power island manager in communication with at least one of the power islands; and an adaptive leakage controller configured to control change of a variable voltage to be applied to the sleep transistors, and the power island manager configured to generate the variable voltage based on a control signal received from the adaptive leakage controller. - View Dependent Claims (65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77)
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78. An integrated circuit comprising:
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a plurality of power islands having associated power consumptions, and the power consumptions being dynamically changeable based on needs and operation of the integrated circuit, and each of the power islands including circuitries and sleep transistors in coupled relation with the circuitries, and the sleep transistors being included within the integrated circuit to facilitate reduction of power consumed by the circuitries; a sleep generator including a charge pump to generate a variable voltage to be applied to the sleep transistors; and an adaptive leakage controller configured to control change of the variable voltage by providing a digital control signal to the sleep generator. - View Dependent Claims (79, 80, 81, 82)
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Specification
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- Resources
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Current AssigneeMosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
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Original AssigneeMosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
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InventorsCole, Andrew, Callahan, John M., Walker, William G., Zampaglione, Michael A., Hoberman, Barry A., Hillman, Daniel L.
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Granted Patent
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Time in Patent OfficeDays
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Field of Search
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US Class Current327/544
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CPC Class CodesG11C 5/14 Power supply arrangements ,...G11C 5/144 Detection of predetermined ...G11C 5/148 Details of power up or powe...H02M 3/07 using capacitors charged an...H03K 17/102 in field-effect transistor ...H03K 19/0016 by using a control or a clo...H03K 19/00315 in field-effect transistor ...H03K 3/0372 of the master-slave typeH03K 3/356086 with additional means for c...H03K 3/356113 using additional transistor...H03K 5/14 by the use of delay lines H...
