TRANSACTION PROCESSING MULTIPLE PROTOCOL ENGINES IN SYSTEMS HAVING MULTIPLE MULTI-PROCESSOR CLUSTERS

US 20120089787A1
Filed: 12/15/2011
Published: 04/12/2012
Est. Priority Date: 11/05/2002
Status: Active Grant

First Claim

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1. A computer system comprising a plurality of processor clusters, each cluster including a plurality of local nodes and an interconnection controller interconnected by a local point-to-point architecture, wherein the interconnection controller in each cluster comprises a plurality of protocol engines for processing transactions, and wherein at least one of the interconnection controller and the local nodes in each cluster is operable to map the transactions to the protocol engines according to destination information associated with the transactions.

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Abstract

A multi-processor computer system is described in which transaction processing in each cluster of processors is distributed among multiple protocol engines. Each cluster includes a plurality of local nodes and an interconnection controller interconnected by a local point-to-point architecture. The interconnection controller in each cluster comprises a plurality of protocol engines for processing transactions. Transactions are distributed among the protocol engines using destination information associated with the transactions.

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30 Claims

1. A computer system comprising a plurality of processor clusters, each cluster including a plurality of local nodes and an interconnection controller interconnected by a local point-to-point architecture, wherein the interconnection controller in each cluster comprises a plurality of protocol engines for processing transactions, and wherein at least one of the interconnection controller and the local nodes in each cluster is operable to map the transactions to the protocol engines according to destination information associated with the transactions.
- View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
- - 2. The computer system of claim 1 wherein the plurality of protocol engines in each interconnection controller comprises at least one remote protocol engine for processing transactions targeting remote memory and at least one local protocol engine for processing transactions targeting local memory.
  - 3. The computer system of claim 2 wherein the destination information employed by one of a first interconnection controller and a first node in a first cluster for a first transaction directed to a second cluster comprises a target address corresponding to a packet associated with the first transaction.
  - 4. The computer system of claim 3 wherein the at least one remote protocol engine and at least one local protocol engine in each interconnection controller comprise a plurality of remote protocol engines and a plurality of local protocol engines, and wherein the one of the first interconnection controller and the first node is operable to map the first transaction to one of the protocol engines with reference to at least one bit in the target address.
  - 5. The computer system of claim 4 wherein the at least one bit corresponds to either a memory line boundary or a memory page boundary.
  - 6. The computer system of claim 3 wherein the first interconnection controller is further operable to map a local node identifier in the packet to a destination node identifier corresponding to the second cluster.
  - 7. The computer system of claim 6 wherein a second interconnection controller associated with the second cluster is operable to use the destination node identifier to map the first transaction to one of its associated protocol engines.
  - 8. The computer system of claim 3 wherein the target address is in the packet.
  - 9. The computer system of claim 3 wherein the target address is in memory associated with the first interconnection controller, the first interconnection controller being operable to retrieve the target address with reference to a transaction identifier in the packet.
  - 10. The computer system of claim 2 wherein the destination information employed by a first interconnection controller in a first cluster for a first transaction directed to the first cluster comprises a destination node identifier in a packet associated with the first transaction, the destination node identifier corresponding to a local node in the first cluster to which the first transaction is directed.
  - 11. The computer system of claim 10 wherein the at least one local protocol engine and at least one remote protocol engine in each interconnection controller comprises a plurality of local protocol engines and a plurality of remote protocol engines each of which corresponds to one of the associated local nodes, and wherein the first interconnection controller is operable to map the first transaction to one of the protocol engines with reference to the destination node identifier.
  - 12. The computer system of claim 11 wherein the packet originated in a second cluster having a second interconnection controller associated therewith, the second interconnection controller being operable to map a local node identifier in the packet corresponding to the second cluster to the destination node identifier.
  - 13. The computer system of claim 1 wherein the plurality of protocol engines in each interconnection controller comprises a plurality of remote protocol engines for processing transactions targeting remote memory and a plurality of local protocol engines for processing transactions targeting local memory.
  - 14. The computer system of claim 13 wherein the destination information employed by one of a first interconnection controller and a first node in a first cluster to map a first transaction directed to a second cluster to one of the associated protocol engines comprises a target address corresponding to a first packet associated with the first transaction, and wherein the destination information employed by the first interconnection controller to map a second transaction directed to the first cluster comprises a destination node identifier in a second packet associated with the second transaction, the destination node identifier corresponding to a local node in the first cluster to which the second transaction is directed.
  - 15. The computer system of claim 1 wherein the destination information comprises target addresses associated with the transactions, the transactions being distributed over the associated protocol engines by interleaving the target addresses.
  - 16. The computer system of claim 1 wherein the interconnection controllers are further operable to facilitate cache coherency across the computer system.
  - 17. The computer system of claim 1 wherein each cluster has a local transaction space associated therewith for uniquely identifying locally generated transactions within the cluster, and wherein the interconnection controller in each cluster is operable to uniquely map selected ones of locally generated transactions directed to others of the clusters to a global transaction space, and remotely generated transactions directed to the associated local nodes to the local transaction space.
  - 18. The computer system of claim 1 wherein the interconnection controller in each cluster is further operable to map locally generated address information to others of the clusters, and remotely generated address information to the associated local nodes.
  - 19. The computer system of claim 1 wherein the point-to-point architecture comprises a plurality of local point-to-point links and wherein the plurality of clusters are interconnected with a plurality of global links, the interconnection controller in each cluster further being operable using global routing information to map locally generated transmissions directed to others of the clusters to the global links, and using local routing information to map remotely generated transmissions directed to the local nodes to the local links.
  - 20. The computer system of claim 1 wherein a first transaction corresponds to a packet generated by a first local node in a first cluster, the packet including a node identifier corresponding to a first one of the protocol engines associated with the interconnection controller in the first cluster, the first transaction being mapped to the first protocol engine by the first local node generating the node identifier with reference to a target address associated with the first transaction.
  - 21. The computer system of claim 1 wherein a first transaction corresponds to a packet generated by a first local node in a first cluster, the packet including a target address, the first transaction being mapped by the interconnection controller in the first cluster to one of the associated protocol engines with reference to the target address.

22. An interconnection controller for use in a computer system having a plurality of processor clusters, each cluster including a plurality of local nodes and an instance of the interconnection controller interconnected by a local point-to-point architecture, the interconnection controller comprising a plurality of protocol engines for processing transactions, and circuitry which is operable to map the transactions to the protocol engines using destination information associated with the transactions.
- View Dependent Claims (23, 24, 25, 26, 27, 28, 29, 30)
- - 23. An integrated circuit comprising the interconnection controller of claim 22.
  - 24. The integrated circuit of claim 23 wherein the integrated circuit comprises an application-specific integrated circuit.
  - 25. At least one computer-readable medium having data structures stored therein representative of the interconnection controller of claim 22.
  - 26. The at least one computer-readable medium of claim 25 wherein the data structures comprise a simulatable representation of the interconnection controller.
  - 27. The at least one computer-readable medium of claim 26 wherein the simulatable representation comprises a netlist.
  - 28. The at least one computer-readable medium of claim 25 wherein the data structures comprise a code description of the interconnection controller.
  - 29. The at least one computer-readable medium of claim 28 wherein the code description corresponds to a hardware description language.
  - 30. A set of semiconductor processing masks representative of at least a portion of the interconnection controller of claim 22.

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Current Assignee
Sanmina-SCI Corporation
Original Assignee
Memory Integrity LLC
Inventors
Kota, Rajesh, Glasco, David Brian, Watson, Charles Edward Jr.

Granted Patent

US 8,572,206 B2
Time in Patent Office

Days
Field of Search
US Class Current

711/141
CPC Class Codes

G06F 12/0815   Cache consistency protocols

G06F 13/4022   using switching circuits, e...

G06F 15/17337   Direct connection machines,...

G06F 15/80   comprising an array of proc...

G06F 2212/621   Coherency control relating ...

H04L 69/12   Protocol engines

H04L 69/18   Multiprotocol handlers, e.g...

TRANSACTION PROCESSING MULTIPLE PROTOCOL ENGINES IN SYSTEMS HAVING MULTIPLE MULTI-PROCESSOR CLUSTERS

First Claim

7 Assignments

0 Petitions

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Abstract

10 Citations

30 Claims

Specification

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TRANSACTION PROCESSING MULTIPLE PROTOCOL ENGINES IN SYSTEMS HAVING MULTIPLE MULTI-PROCESSOR CLUSTERS

First Claim

7 Assignments

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0 Petitions

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Accused Products

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Abstract

10 Citations

30 Claims

Specification

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Solutions

Use Cases

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