Three dimensional memory structure

US 20130320341A1
Filed: 08/09/2013
Published: 12/05/2013
Est. Priority Date: 04/04/1997
Status: Active Grant

First Claim

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1. A stacked circuit structure comprising:

a plurality of stacked, thinned, substantially flexible circuit layers or wiring layers each comprising a top surface and a bottom surface and at least one of which comprises a thinned, substantially flexible semiconductor substrate of one piece; and

an interlayer region disposed between a pair of vertically adjacent circuit layers or wiring layers and extending from a top surface of one of the pair of vertically adjacent circuit layers or wiring layers to a bottom surface of another one of the pair of vertically adjacent circuit layers or wiring layers, the interlayer region comprising an interlayer for providing mechanical attachment and electrical interconnection between the pair of vertically adjacent circuit layers or wiring layers;

wherein within the interlayer region the stacked circuit structure consists essentially of metal or metal and silicon-based dielectric.

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Abstract

A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 microns in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

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31 Claims

1. A stacked circuit structure comprising:
- a plurality of stacked, thinned, substantially flexible circuit layers or wiring layers each comprising a top surface and a bottom surface and at least one of which comprises a thinned, substantially flexible semiconductor substrate of one piece; and
  
  an interlayer region disposed between a pair of vertically adjacent circuit layers or wiring layers and extending from a top surface of one of the pair of vertically adjacent circuit layers or wiring layers to a bottom surface of another one of the pair of vertically adjacent circuit layers or wiring layers, the interlayer region comprising an interlayer for providing mechanical attachment and electrical interconnection between the pair of vertically adjacent circuit layers or wiring layers;
  
  wherein within the interlayer region the stacked circuit structure consists essentially of metal or metal and silicon-based dielectric.
- View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 20)
- - 2. The apparatus of claim 1, wherein the interlayer comprises both signal-carrying metal contacts and non-signal-carrying metal bonding areas.
  - 3. The apparatus of claim 1, wherein the thinned, substantially flexible semiconductor substrate comprises a plurality of etched through-holes each surrounding a vertical interconnect, each vertical interconnect comprising a conductor and an insulator surrounding the conductor and isolating the conductor from the thinned, substantially flexible semiconductor substrate.
  - 4. The apparatus of claim 3, wherein the insulator comprises low-stress dielectric material having a stress of 5×
    - 10⁸dynes/cm²tensile or less.
  - 5. The apparatus of claim 1, comprising a low-stress dielectric layer formed above the thinned, substantially flexible semiconductor substrate, wherein the low-stress dielectric layer exhibits net tensile stress.
  - 6. The apparatus of claim 5, wherein the low-stress dielectric layer has a stress of 5×
    - 10⁸dynes/cm²tensile or less.
  - 7. The apparatus of claim 1, wherein a backside of the thinned, substantially flexible semiconductor substrate is polished to reduce vulnerability to fracture as a result of flexing and is devoid of integrated circuitry.
  - 8. The apparatus of claim 1, comprising a plurality of stacked, thinned, substantially flexible circuit layers, one of the stacked, thinned, substantially flexible circuit layers comprising a memory array and another of the stacked, thinned, substantially flexible circuit layers comprising a memory controller for controlling the memory array.
  - 9. The apparatus of claim 8, wherein the one of the stacked, thinned, substantially flexible circuit layers comprises a plurality of independently-operable memory arrays, the memory controller being configured to control the plurality of independently-operable memory arrays independently and in parallel;
    - further comprising a plurality of independently-operable vertical interconnect buses, wherein data exchanged between the memory controller and the plurality of independently-operable memory arrays is bussed independently and in parallel over the plurality of independently-operable vertical interconnect buses.
  - 10. The apparatus of claim 8, wherein at least one of:
    - the memory array and memory controller together form a memory, the memory being reconfigurable by operation of the memory controller;
      
      the other of the stacked, thinned, substantially flexible circuit layers comprises circuitry for performing functional testing of the memory array.
  - 20. The apparatus of claim 8, wherein at least one of:
    - the memory array and memory controller together form a memory, the memory being reconfigurable by operation of the memory controller;
      
      the other of the stacked, thinned, substantially flexible circuit layers comprises circuitry for performing functional testing of the memory array.

11. A stacked circuit structure comprising:
- a plurality of stacked, thinned, substantially flexible circuit layers or wiring layers each comprising a top surface and a bottom surface and at least one of which comprises a thinned, substantially flexible semiconductor substrate of one piece;
  
  wherein a pair of vertically adjacent circuit layers or wiring layers is joined together using metal-to-metal bonding as a sole or primary mechanism of both attachment and electrical interconnection.
- View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19)
- - 12. The apparatus of claim 11, comprising an interlayer joining the pair of vertically adjacent circuit layers or wiring layers, the interlayer comprising both signal-carrying metal contacts and non-signal-carrying metal bonding areas.
  - 13. The apparatus of claim 11, wherein the thinned, substantially flexible semiconductor substrate comprises a plurality of etched through-holes each surrounding a vertical interconnect, each vertical interconnect comprising a conductor and an insulator surrounding the conductor and isolating the conductor from the thinned, substantially flexible semiconductor substrate.
  - 14. The apparatus of claim 13, wherein the insulator comprises low-stress dielectric material having a stress of 5×
    - 10⁸dynes/cm²tensile or less.
  - 15. The apparatus of claim 11, comprising a low-stress dielectric layer formed above the thinned, substantially flexible semiconductor substrate, wherein the low-stress dielectric layer exhibits net tensile stress.
  - 16. The apparatus of claim 15, wherein the low-stress dielectric layer has a stress of 5×
    - 10⁸dynes/cm²tensile or less.
  - 17. The apparatus of claim 11, wherein a backside of the thinned, substantially flexible semiconductor substrate is polished to reduce vulnerability to fracture as a result of flexing and is devoid of integrated circuitry.
  - 18. The apparatus of claim 11, comprising a plurality of stacked, thinned, substantially flexible circuit layers, one of the stacked, thinned, substantially flexible circuit layers comprising a memory array and another of the stacked, thinned, substantially flexible circuit layers comprising a memory controller for controlling the memory array.
  - 19. The apparatus of claim 18, wherein the one of the stacked, thinned, substantially flexible circuit layers comprises a plurality of independently-operable memory arrays, the memory controller being configured to control the plurality of independently-operable memory arrays independently and in parallel;
    - further comprising a plurality of independently-operable vertical interconnect buses, wherein data exchanged between the memory controller and the plurality of independently-operable memory arrays is bussed independently and in parallel over the plurality of independently-operable vertical interconnect buses.

21. A stacked circuit structure comprising:
- a plurality of stacked, thinned, substantially flexible circuit layers or wiring layers each comprising a top surface and a bottom surface and at least one of which comprises a thinned, substantially flexible semiconductor substrate of one piece;
  
  wherein a pair of adjacent ones of the stacked, thinned, substantially flexible circuit layers or wiring layers is bonded together at least predominantly with metal, or at least predominantly with silicon-based dielectric and metal;
- View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29)
- - 22. The apparatus of claim 21, comprising an interlayer joining the pair of adjacent ones of the stacked, thinned, substantially flexible circuit layers or wiring layers, the interlayer comprising signal-carrying metal contacts and non-signal-carrying metal bonding areas.
  - 23. The apparatus of claim 21, wherein the thinned, substantially flexible semiconductor substrate comprises a plurality of etched through-holes each surrounding a vertical interconnect, each vertical interconnect comprising a conductor and an insulator surrounding the conductor and isolating the conductor from the thinned, substantially flexible semiconductor substrate.
  - 24. The apparatus of claim 23, wherein the insulator comprises low-stress dielectric material having a stress of 5×
    - 10⁸dynes/cm²tensile or less.
  - 25. The apparatus of claim 21, comprising a low-stress dielectric layer formed above the thinned, substantially flexible semiconductor substrate, wherein the low-stress dielectric layer exhibits net tensile stress.
  - 26. The apparatus of claim 25, wherein the low-stress dielectric layer has a stress of 5×
    - 10⁸dynes/cm²tensile or less.
  - 27. The apparatus of claim 21, wherein a backside of the thinned, substantially flexible semiconductor substrate is polished to reduce vulnerability to fracture as a result of flexing and is devoid of integrated circuitry.
  - 28. The apparatus of claim 21, comprising a plurality of stacked, thinned, substantially flexible circuit layers, one of the stacked, thinned, substantially flexible circuit layers comprising a memory array and another of the stacked, thinned, substantially flexible circuit layers comprising a memory controller for controlling the memory array.
  - 29. The apparatus of claim 28, wherein the one of the stacked, thinned, substantially flexible circuit layers comprises a plurality of independently-operable memory arrays, the memory controller being configured to control the plurality of independently-operable memory arrays independently and in parallel;
    - further comprising a plurality of independently-operable vertical interconnect buses, wherein data exchanged between the memory controller and the plurality of independently-operable memory arrays is bussed independently and in parallel over the plurality of independently-operable vertical interconnect buses.

30. (canceled)

31. A stacked circuit structure comprising:
- a plurality of stacked, thinned, substantially flexible circuit layers or wiring layers each comprising a top surface and a bottom surface and at least one of which comprises a thinned, substantially flexible semiconductor substrate of one piece;
  
  wherein a plurality of the substantially flexible circuit layers are formed of polysilicon and a low stress silicon-based dielectric material; and
  
  at least one vertical interconnection that passes through a plurality of the substantially flexible circuit layers.

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Current Assignee
Elm 3DS Innovations LLC
Original Assignee
Elm 3DS Innovations LLC
Inventors
Leedy, Glenn J.

Granted Patent

US 8,796,862 B2
Time in Patent Office

Days
Field of Search
US Class Current

257/48
CPC Class Codes

G11C 5/02   Disposition of storage elem...

G11C 5/06   Arrangements for interconne...

H01L 21/76898   formed through a semiconduc...

H01L 2224/8083   Solid-solid interdiffusion

H01L 2224/8384   Sintering

H01L 23/481   Internal lead connections, ...

H01L 23/5226   Via connections in a multil...

H01L 25/0657   Stacked arrangements of dev...

H01L 27/0688   Integrated circuits having ...

H01L 29/02   Semiconductor bodies ; Mult...

H01L 2924/01079   Gold [Au]

H10B 12/50   Peripheral circuit region s...

Y10S 438/977   Thinning or removal of subs...

Three dimensional memory structure

First Claim

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Abstract

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31 Claims

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Three dimensional memory structure

First Claim

4 Assignments

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0 Petitions

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Accused Products

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Abstract

5 Citations

31 Claims

Specification

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Solutions

Use Cases

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