Three dimensional memory structure
First Claim
Patent Images
1. A circuit layer comprising:
- a semiconductor substrate of one piece;
interconnect conductors passing vertically through the semiconductor substrate; and
dielectric insulators passing vertically through the semiconductor substrate around the vertical interconnect conductors, the dielectric insulators having a stress of about 5×
108 dynes/cm2 or less.
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Accused Products
Abstract
A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 microns in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.
0 Citations
30 Claims
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1. A circuit layer comprising:
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a semiconductor substrate of one piece; interconnect conductors passing vertically through the semiconductor substrate; and dielectric insulators passing vertically through the semiconductor substrate around the vertical interconnect conductors, the dielectric insulators having a stress of about 5×
108 dynes/cm2 or less. - View Dependent Claims (2, 3, 4, 5, 6)
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7. The circuit layer of claim 7, wherein:
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the semiconductor substrate has holes vertically etched therethrough; and the interconnect conductors and the dielectric insulators pass through the holes.
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8. A substantially flexible circuit layer comprising:
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a semiconductor substrate of one piece that is thinned and substantially flexible; a dielectric film on the semiconductor substrate, the dielectric film having a stress of about 5×
108 dynes/cm2 or less;interconnect conductors passing vertically through the semiconductor substrate; and dielectric insulators around the vertical interconnect conductors and passing vertically through the semiconductor substrate, the dielectric insulators having a stress of about 5×
108 dynes/cm2 or less. - View Dependent Claims (9, 10, 11, 12, 13)
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14. A stacked substrate structure comprising:
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a first circuit layer comprising contacts, interconnects, or circuitry; and a second circuit layer stacked with the first circuit layer, the second circuit layer comprising; a semiconductor substrate of one piece; contacts, interconnects or circuitry integrated with the semiconductor substrate; interconnect conductors extending vertically through the semiconductor substrate and connected between the contacts, interconnects, or circuitry of the second circuit layer and the contacts, interconnects, or circuitry of the first circuit layer; and dielectric insulators around the interconnect conductors and passing vertically through the semiconductor substrate, the dielectric insulators having a stress of about 5×
108 dynes/cm2 or less. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22)
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23. An integrated circuit structure comprising:
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a first circuit layer comprising contacts, interconnects, or circuitry; and a second circuit layer stacked with the first circuit layer, the second circuit layer being substantially flexible and comprising; a semiconductor substrate of one piece that is thinned and substantially flexible; a dielectric film on the semiconductor substrate and having a stress of about 5×
108 dynes/cm2 or less;contacts, interconnects, or circuitry integrated with the semiconductor substrate and the dielectric film; interconnect conductors passing vertically through the semiconductor substrate and connected between the contacts, interconnects, or circuitry of the second circuit layer and the contacts, interconnects, or circuitry of the first circuit layer; and dielectric insulators around the interconnect conductors and passing vertically through the semiconductor substrate, the dielectric insulators having a stress of about 5×
108 dynes/cm2 or less. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30)
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Specification
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Current AssigneeElm 3DS Innovations LLC
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Original AssigneeElm 3DS Innovations LLC
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InventorsLeedy, Glenn J.
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Granted Patent
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Time in Patent OfficeDays
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Field of Search
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US Class Current257/774
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CPC Class CodesG11C 5/02 Disposition of storage elem...G11C 5/06 Arrangements for interconne...H01L 21/76898 formed through a semiconduc...H01L 2224/8083 Solid-solid interdiffusionH01L 2224/8384 SinteringH01L 23/481 Internal lead connections, ...H01L 23/5226 Via connections in a multil...H01L 25/0657 Stacked arrangements of dev...H01L 27/0688 Integrated circuits having ...H01L 29/02 Semiconductor bodies ; Mult...H01L 2924/01079 Gold [Au]H10B 12/50 Peripheral circuit region s...Y10S 438/977 Thinning or removal of subs...
