Three dimensional structure memory
First Claim
Patent Images
1. A stacked memory integrated circuit comprising:
- a plurality of circuit layers comprising at least one control circuit layer and at least one memory circuit layer arranged in a stacked relationship;
wherein the control and memory circuit layers of the stacked memory integrated circuit are partitioned into a plurality of vertically interconnected circuit blocks and configured for a plurality of said vertically interconnected circuit blocks to independently perform memory operations.
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Accused Products
Abstract
A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 microns in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.
4 Citations
30 Claims
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1. A stacked memory integrated circuit comprising:
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a plurality of circuit layers comprising at least one control circuit layer and at least one memory circuit layer arranged in a stacked relationship; wherein the control and memory circuit layers of the stacked memory integrated circuit are partitioned into a plurality of vertically interconnected circuit blocks and configured for a plurality of said vertically interconnected circuit blocks to independently perform memory operations. - View Dependent Claims (2, 3, 4, 17, 18, 19, 20, 21, 22, 23)
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5. A stacked memory integrated circuit comprising:
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a plurality of circuit layers comprising at least one control circuit layer and at least one memory circuit layer arranged in a stacked relationship; wherein the control and memory circuit layers of the stacked memory integrated circuit are partitioned into a plurality of vertically interconnected circuit blocks and configured for a plurality of said vertically interconnected circuit blocks to independently and simultaneously perform memory operations. - View Dependent Claims (6, 7, 8, 24, 25, 26, 27, 28, 29, 30)
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9. A method of information processing using a stacked memory integrated circuit comprising a plurality of circuit layers comprising at least one control circuit layer and at least one memory circuit layer arranged in a stacked relationship, wherein the control and memory circuit layers of the stacked memory integrated circuit are partitioned into a plurality of vertically interconnected circuit blocks of control and memory circuitry and configured for a plurality of said vertically interconnected circuit blocks to independently and simultaneously perform memory operations, the method comprising:
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control circuitry of a first memory block receiving a first memory address, and control circuitry of a second memory block receiving a second memory address; and the control circuitry of the first memory block reading or writing one or more memory locations corresponding to said first memory address of the memory circuitry, and at least partly simultaneously, the control circuitry of the second memory block reading or writing one or more memory locations corresponding to said second memory address of the memory circuitry. - View Dependent Claims (10, 11)
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12. A stacked memory integrated circuit comprising:
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a first integrated circuit controller layer; at least one low stress dielectric layer formed over the first integrated circuit controller layer and having a tensile stress of about 5×
108 dynes/cm2 tensile or less; anda plurality of semiconductor memory layers overlaying the first integrated circuit controller layer; wherein at least one vertical interconnection passes through a majority of the semiconductor memory layers, a majority of the at least one vertical interconnection being insulated by a dielectric material having a tensile stress of about 5×
108 dynes/cm2 or less. - View Dependent Claims (13, 14, 15, 16)
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Specification
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Current AssigneeElm 3DS Innovations LLC
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Original AssigneeElm 3DS Innovations LLC
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InventorsLeedy, Glenn J.
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Granted Patent
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Time in Patent OfficeDays
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Field of Search
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US Class Current365/51
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CPC Class CodesG11C 5/02 Disposition of storage elem...G11C 5/06 Arrangements for interconne...H01L 21/76898 formed through a semiconduc...H01L 2224/8083 Solid-solid interdiffusionH01L 2224/8384 SinteringH01L 23/481 Internal lead connections, ...H01L 23/5226 Via connections in a multil...H01L 25/0657 Stacked arrangements of dev...H01L 27/0688 Integrated circuits having ...H01L 29/02 Semiconductor bodies ; Mult...H01L 2924/01079 Gold [Au]H10B 12/50 Peripheral circuit region s...Y10S 438/977 Thinning or removal of subs...
