Method and apparatus for translating virtual addresses in a data processing system having multiple instruction pipelines and separate TLB's
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First Claim
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1. An apparatus for translating virtual addresses in a computing system having at least a first and a second instruction pipeline and a direct address translation unit for translating virtual addresses into real addresses, the direct address translation unit including a master translation memory for storing translation data, the direct address translation unit for translating a virtual address into a corresponding real address, comprising:
- a first translation buffer, associated with the first instruction pipeline, for storing a first subset of translation data from the master translation memory;
a first address translator, coupled to the first instruction pipeline and to the first translation buffer, for translating a first virtual address received from the first instruction pipeline into a corresponding first real address, the first address translator comprising;
first translation buffer accessing means for accessing the first translation buffer;
first translation indicating means, coupled to the first translation buffer accessing means, for indicating whether translation data for the first virtual address is stored in the first translation buffer; and
first direct address translating means, coupled to the first translation indicating means and to the direct address translation unit to translate the first virtual address when the first translation indicating means indicates that the translation data for the first virtual address is not stored in the first translation buffer, the first direct address translating means including first translation buffer storing means, coupled to the first translation buffer, for storing the translation data for the first virtual address from the master translation memory into the first translation buffer;
a second translation buffer, associated with the second instruction pipeline, for storing a second subset of translation data from the master translation memory; and
a second address translator, coupled to the second instruction pipeline and to the second translation buffer, for translating a second virtual address received from the second instruction pipeline into a corresponding second real address, the second address translator comprising;
second translation buffer accessing means for accessing the second translation buffer;
second translation indicating means, coupled to the second translation buffer accessing means, for indicating whether translation data for the second virtual address is stored in the second translation buffer; and
second direct address translating means, coupled to the second translation indicating means and to the first address translation unit, for activating the direct address translation unit to translate the second virtual address when the second translation indicating means indicates that the translation data for the second virtual address is not stored in the second translation buffer, the second direct address translating means including second translation buffer storing means, coupled to the second translation buffer, for storing the translation data for the second virtual address from the master translation memory into the second translation buffer.
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Abstract
A computing system has multiple instruction pipelines, wherein one or more pipelines require translating virtual addresses to real addresses. A TLB is provided for each pipeline requiring address translation services, and an adress translator is provided for each such pipeline for translating a virtual address recieved from its associated pipeline into corresponding real addresses. Each address translator comprises a translation buffer accessing circuit for accessing the TLB, a translation indicating circuit for indicating whether translation data for the virtual address is stored in the translation buffer, and an update control circuit for activating the direct address translation circuit when the translation data for the virtual address is not stored in the TLB. The update control circuit also stores the translation data retrieved from the main memory into the TLB. If it is desired to have the same translation information available for all the pipelines in a group, then the update control circuit also updates all the other TLB'"'"'s in the group.
27 Citations
14 Claims
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1. An apparatus for translating virtual addresses in a computing system having at least a first and a second instruction pipeline and a direct address translation unit for translating virtual addresses into real addresses, the direct address translation unit including a master translation memory for storing translation data, the direct address translation unit for translating a virtual address into a corresponding real address, comprising:
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a first translation buffer, associated with the first instruction pipeline, for storing a first subset of translation data from the master translation memory; a first address translator, coupled to the first instruction pipeline and to the first translation buffer, for translating a first virtual address received from the first instruction pipeline into a corresponding first real address, the first address translator comprising; first translation buffer accessing means for accessing the first translation buffer; first translation indicating means, coupled to the first translation buffer accessing means, for indicating whether translation data for the first virtual address is stored in the first translation buffer; and first direct address translating means, coupled to the first translation indicating means and to the direct address translation unit to translate the first virtual address when the first translation indicating means indicates that the translation data for the first virtual address is not stored in the first translation buffer, the first direct address translating means including first translation buffer storing means, coupled to the first translation buffer, for storing the translation data for the first virtual address from the master translation memory into the first translation buffer; a second translation buffer, associated with the second instruction pipeline, for storing a second subset of translation data from the master translation memory; and a second address translator, coupled to the second instruction pipeline and to the second translation buffer, for translating a second virtual address received from the second instruction pipeline into a corresponding second real address, the second address translator comprising; second translation buffer accessing means for accessing the second translation buffer; second translation indicating means, coupled to the second translation buffer accessing means, for indicating whether translation data for the second virtual address is stored in the second translation buffer; and second direct address translating means, coupled to the second translation indicating means and to the first address translation unit, for activating the direct address translation unit to translate the second virtual address when the second translation indicating means indicates that the translation data for the second virtual address is not stored in the second translation buffer, the second direct address translating means including second translation buffer storing means, coupled to the second translation buffer, for storing the translation data for the second virtual address from the master translation memory into the second translation buffer. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method for translating virtual addresses in a computing system having at least a first and a second instruction pipeline and a direct address translation unit for translating virtual addresses into real addresses, the direct address translation unit including a master translation memory for storing translation data, the direct address translation unit for translating a virtual address into a corresponding real address, comprising the steps of:
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storing a first subset of translation data from the master translation memory into a first translation buffer associated with the first instruction pipeline; translating a first virtual address received from the first instruction pipeline into a corresponding first real address, wherein the first virtual address translating step comprises the steps of; accessing the first translation buffer; indicating whether translation data for the first virtual address is stored in the first translation buffer; activating the direct address translation unit to translate the first virtual address when the translation data for the first virtual address is not stored in the first translation buffer; and storing the translation data for the first virtual address from the master translation memory into the first translation buffer; storing a second subset of translation data from the master translation memory into a second translation buffer associated with the second instruction pipeline; and translating a second virtual address received from the second instruction pipeline into a corresponding second real address, wherein the second virtual address translating step comprises the steps of; accessing the second translation buffer; indicating whether translation data for the second virtual address is stored in the second translation buffer; activating the direct address translation unit to translate the second virtual address when the translation data for the second virtual address is not stored in the second translation buffer; and storing the translation data for the second virtual address from the master translation memory into the second translation buffer. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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Specification
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Litigation Data
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Current AssigneeVantage Point Technology, Inc. (Marathon Patent Group, Inc.)
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Original AssigneeIntergraph Corporation (Hexagon AB)
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InventorsSachs, Howard G.
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Primary Examiner(s)Kim, Ken S.
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Application NumberUS08/146,818Time in Patent Office728 DaysField of Search395/400, 395/425, 395/800US Class Current711/169CPC Class CodesG06F 12/1027 using associative or pseudo...G06F 9/3824 Operand accessingG06F 9/3877 using a slave processor, e....
