Method of fabricating thin film transistor array
DC CAFC
First Claim
1. A method of fabricating a thin film transistor array comprising a transparent insulating substrate, a plurality of thin film transistors formed on said substrate in a matrix, a gate bus line connected to gate electrodes of said thin film transistors, a drain bus line connected to drain electrodes of said thin film transistors, and a pixel electrode driven by said thin film transistors, said method comprising the steps of:
- (a) forming said gate electrodes and said gate bus line on said transparent insulating substrate;
(b) forming a gate insulating film over said substrate;
(c) forming an operative semiconductor on said gate insulating film;
(d) forming source electrodes, said drain electrodes, and said drain bus line of said thin film transistors on said gate insulating film and said operative semiconductor;
(e) forming a protection film over said substrate;
(f) removing a portion of both said gate insulating film and said protection film, located above a terminal of said gate bus line, and removing a portion of said protection film located above a terminal of said drain bus line; and
(g) forming said pixel electrode on said substrate.
4 Assignments
Litigations
1 Petition
Accused Products
Abstract
There is provided a method of fabricating a thin film transistor array having a transparent insulating substrate, a plurality of thin film transistors formed on the substrate in a matrix, a gate bus line connected to gate electrodes of the thin film transistors, a drain bus line connected to drain electrodes of the thin film transistors, and a pixel electrode driven by the thin film transistors, the method including the steps of forming the gate electrode and the gate bus line on the transparent insulating substrate, forming a gate insulating film over the substrate, forming an operative semiconductor on the gate insulating film, forming the source electrodes, drain electrodes, and drain bus line of the thin film transistors on the gate insulating film and the operative semiconductor, forming a protection film all over the substrate, removing a portion of both the gate insulating film and the protection film, located above a terminal of the gate bus line, and also removing a portion of the protection film located above a terminal of the drain bus line, and forming the pixel electrode on the substrate. The above-mentioned method makes it possible to make a gate bus line and a drain bus line appear by only one photolithography step. Hence, the above-mentioned method needs to carry out only five photolithography steps to fabricate a thin film transistor array, whereas the conventional methods have to carry out six photolithography steps.
24 Citations
11 Claims
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1. A method of fabricating a thin film transistor array comprising a transparent insulating substrate, a plurality of thin film transistors formed on said substrate in a matrix, a gate bus line connected to gate electrodes of said thin film transistors, a drain bus line connected to drain electrodes of said thin film transistors, and a pixel electrode driven by said thin film transistors, said method comprising the steps of:
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(a) forming said gate electrodes and said gate bus line on said transparent insulating substrate; (b) forming a gate insulating film over said substrate; (c) forming an operative semiconductor on said gate insulating film; (d) forming source electrodes, said drain electrodes, and said drain bus line of said thin film transistors on said gate insulating film and said operative semiconductor; (e) forming a protection film over said substrate; (f) removing a portion of both said gate insulating film and said protection film, located above a terminal of said gate bus line, and removing a portion of said protection film located above a terminal of said drain bus line; and (g) forming said pixel electrode on said substrate. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method of fabricating a thin film transistor array comprising a transparent insulating substrate, a plurality of thin film transistors formed on said substrate in a matrix, a gate bus line connected to gate electrodes of said thin film transistors, a drain bus line connected to drain electrodes of said thin film transistors, an auxiliary capacitive bus line, and a pixel electrode driven by said thin film transistors, said thin film transistor array controlling liquid crystal by a horizontal field produced between said pixel electrode and said auxiliary capacitive bus line, said method comprising the steps of:
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(a) forming said gate electrodes, said gate bus line, and said auxiliary capacitive bus line on said transparent insulating substrate, and a first transparent electrode on said gate electrode and said auxiliary capacitive bus line; (b) forming a gate insulating film over said substrate; (c) forming an operative semiconductor on said gate insulating film; (d) forming (d-1) said drain electrodes and said drain bus line of said thin film transistors on said gate insulating film and said operative semiconductor, (d-2) said pixel electrode of the same material as material of which said drain electrodes and said drain bus line are formed, and (d-3) a second transparent electrode on said drain electrodes, said drain bus line, and said pixel electrode; (e) forming a protection film all over said substrate; and (f) removing a portion of said protection film located above a terminal of said drain bus line to cause said second transparent electrode to appear, and also removing a portion of said protection film and said gate insulating film both located above a terminal of said auxiliary bus line to cause said first transparent electrode to appear. - View Dependent Claims (8, 9, 10, 11)
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Specification
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- Resources
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Current AssigneeGold Charm Limited (Hon Hai Precision Industry Co., Ltd.)
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Original AssigneeNEC Corporation
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InventorsWatanabe, Takahiko, Sukegawa, Osamu
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Primary Examiner(s)Niebling, John F.
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Assistant Examiner(s)LEBENTRITT, MICHAEL
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Application NumberUS08/989,573Time in Patent Office669 DaysField of Search438/30, 438/158, 438/159US Class Current438/30CPC Class CodesG02F 1/13458 Terminal padsG02F 1/136213 Storage capacitors associat...H01L 27/1214 comprising a plurality of T...H01L 27/1288 employing particular maskin...
