Network processor having cyclic redundancy check implemented in hardware
DC
First Claim
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1. A method for performing a Cyclic Redundancy Check (CRC) operation to generate a CRC result based on input data comprising:
- receiving an instruction indicating the CRC operation is to be executed, the instruction including an indication of a polynomial to use in calculating the CRC result;
selecting one of a plurality of CRC circuits to perform the CRC operation based on the indication of the polynomial in the instruction, each of the plurality of CRC circuits including a CRC polynomial hardwired therein;
receiving the input data at the selected CRC circuit; and
generating the CRC result with the selected CRC circuit.
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Abstract
A network processor [200] performs Cyclic Redundancy Check (CRC) operations using specialized hardware circuits [308-308]. The network processor [200] includes a plurality of hardwired CRC polynomials that are used to implement the CRC operations. A CRC instruction selects which polynomial to use when performing the CRC operation.
14 Citations
11 Claims
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1. A method for performing a Cyclic Redundancy Check (CRC) operation to generate a CRC result based on input data comprising:
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receiving an instruction indicating the CRC operation is to be executed, the instruction including an indication of a polynomial to use in calculating the CRC result; selecting one of a plurality of CRC circuits to perform the CRC operation based on the indication of the polynomial in the instruction, each of the plurality of CRC circuits including a CRC polynomial hardwired therein; receiving the input data at the selected CRC circuit; and generating the CRC result with the selected CRC circuit. - View Dependent Claims (2, 3, 4, 5)
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6. A network processor comprising:
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a bus in communication with a plurality of hardwired Cyclic Redundancy Check (CRC) circuits, each CRC circuit implementing a CRC polynomial for generating a CRC result; and a switch for directing input data to at least one of the CRC circuits based on a CRC instruction; and an error detecting means for determining whether the input data includes an error based on the CRC result. - View Dependent Claims (7, 8, 9)
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10. A network processor comprising:
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a bus in communication with a plurality of preexisting Cyclic Redundancy Check (CRC) circuits, a switch for directing input data to at least one of the CRC circuits based on a CRC instruction based upon an indication of a polynomial included in a CRC instruction; and an error detecting means for determining whether the input data includes an error based on a CRC result output by the at least one CRC circuit to which the input data was directed.
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11. A Cyclic Redundancy Check (CRC) logic unit comprising:
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an input register for storing input data; a plurality of hardwired polynomial circuits for processing the stored input data to generate a CRC result; a switch for directing input data stored in the input register to at least one of the polynomial circuits based on a CRC instruction; and an output register for storing the CRC result.
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Specification
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Litigation Data
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Current AssigneeTAG Foundation (SeeSaw Foundation)
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Original AssigneeBBNT Solutions LLC (Rtx Corporation)
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InventorsMilliken, Walter Clark
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Primary Examiner(s)CHUNG, PHUNG M
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Application NumberUS10/880,281Publication NumberTime in Patent Office651 DaysField of Search714/781, 714/758, 714/807, 714/52, 714/48US Class Current714/781CPC Class CodesH03M 13/09 Error detection only, e.g. ...H03M 13/6513 Support of multiple code ty...H04L 1/0043 Realisations of complexity ...H04L 1/0061 Error detection codesH04L 2001/0094 BusH04L 69/12 Protocol engines
