Methods and apparatus for speculative probing at a request cluster
DCFirst Claim
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1. A computer system, comprising:
- a first cluster including a first plurality of processors and a first cache coherence controller, the first plurality of processors and the first cache coherence controller interconnected in a point-to-point architecture;
a second cluster including a second plurality of processors and a second cache coherence controller, the second plurality of processors and the second cache coherence controller interconnected in a point-to-point architecture, the first cache coherence controller coupled to the second cache coherence controller;
wherein the first cache coherence controller is configured to receive a cache access request originating from the first plurality of processors and send a probe to the first plurality of processors in the first cluster before the cache access request is received by a serialization point in the second cluster.
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Abstract
According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. A cache coherence controller associated with a first cluster of processors can determine whether speculative probing at a first cluster can be performed to improve overall transaction efficiency. Intervening requests from a second cluster can be handled using information from the speculative probe at the first cluster.
36 Citations
52 Claims
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1. A computer system, comprising:
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a first cluster including a first plurality of processors and a first cache coherence controller, the first plurality of processors and the first cache coherence controller interconnected in a point-to-point architecture; a second cluster including a second plurality of processors and a second cache coherence controller, the second plurality of processors and the second cache coherence controller interconnected in a point-to-point architecture, the first cache coherence controller coupled to the second cache coherence controller; wherein the first cache coherence controller is configured to receive a cache access request originating from the first plurality of processors and send a probe to the first plurality of processors in the first cluster before the cache access request is received by a serialization point in the second cluster. - View Dependent Claims (2, 3, 4, 5)
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6. A computer system, comprising:
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a first cluster including a first plurality of processors and a first cache coherence controller, the first plurality of processors and the first cache coherence controller interconnected in a point-to-point architecture; a second cluster including a second plurality of processors and a second cache coherence controller, the second plurality of processors and the second cache coherence controller interconnected in a point-to-point architecture, the first cache coherence controller coupled to the second cache coherence controller and constructed to receive a cache access request originating from the first plurality of processors and send a probe to the first plurality of processors in the first cluster before a memory line associated with the cache access request is locked.
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7. A cache coherence controller, the cache coherence controller comprising:
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interface circuitry coupled to a plurality of local processors in a local cluster and a non-local cache coherence controller in a non-local cluster, wherein the plurality of local processors are arranged in a point-to-point architecture; a protocol engine coupled to the interface circuitry, the protocol engine configured to receive a cache access request from a first processor in the local cluster and speculatively probe a local node. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
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25. A method for a cache coherence controller to manage data access in a multiprocessor system, the method comprising:
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receiving a cache access request from a local processor associated with a local cluster of processors connected through a point-to-point architecture; determining if speculative probing of a local node associated with a cache can be performed before forwarding the cache request to a non-local cache coherence controller, the non-local cache coherence controller associated with a remote cluster of processors connected through a point-to-point architecture, wherein the remote cluster of processors shares an address space with the local cluster of processors. - View Dependent Claims (26, 27, 28, 29, 30, 31, 32, 33)
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34. An apparatus for managing data access in a multiprocessor system, the apparatus comprising:
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means for receiving a cache access request from a local processor associated with a local cluster of processors connected through a point-to-point architecture; means for determining if speculative probing of a local node associated with a cache can be performed before forwarding the cache request to a non-local cache coherence controller, the non-local cache coherence controller associated with a remote cluster of processors connected through a point-to-point architecture, wherein the remote cluster of processors shares an address space with the local cluster of processors. - View Dependent Claims (35, 36, 37, 38, 39, 40, 41)
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42. A system comprising:
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a first cluster having a first processor and a first controller interconnected in a point-to-point architecture; a second cluster having a second processor and a second controller, the first and second processors sharing a common virtual address space, the first and second controllers operable to maintain cache coherency between the first and second clusters by using a speculative probing protocol; and an interconnection network coupling the first and second clusters together to allow communication according to the speculative probing protocol. - View Dependent Claims (43, 44, 45, 46, 47, 48, 49, 50)
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51. A method for a cache coherence controller to manage data access in a multiprocessor system, the method comprising:
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receiving a cache access request originating from a first cluster of processors interconnected with a cache coherence controller in a point-to-point architecture; sending a probe to nodes associated with the first cluster of processors before sending the cache access request to a serialization point in a second cluster of processors.
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52. A method for a cache coherence controller to manage data access in a multiprocessor system, the method comprising:
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receiving a cache access request originating from a first cluster of processors interconnected with a cache coherence controller in a point-to-point architecture; sending a probe to nodes associated with the first cluster of processors before a memory line associated with the cache access request is locked.
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Specification