Reducing probe traffic in multiprocessor systems
DC CAFC
First Claim
1. A computer system comprising a plurality of processing nodes interconnected by a first point-to-point architecture, each processing node having a cache memory associated therewith, the computer system further comprising a probe filtering unit which is operable to receive probes corresponding to memory lines from the processing nodes and to transmit the probes only to selected ones of the processing nodes with reference to probe filtering information representative of states associated with selected ones of the cache memories.
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Accused Products
Abstract
A computer system having a plurality of processing nodes interconnected by a first point-to-point architecture is described. Each processing node has a cache memory associated therewith. A probe filtering unit is operable to receive probes corresponding to memory lines from the processing nodes and to transmit the probes only to selected ones of the processing nodes with reference to probe filtering information. The probe filtering information is representative of states associated with selected ones of the cache memories.
86 Citations
25 Claims
- 1. A computer system comprising a plurality of processing nodes interconnected by a first point-to-point architecture, each processing node having a cache memory associated therewith, the computer system further comprising a probe filtering unit which is operable to receive probes corresponding to memory lines from the processing nodes and to transmit the probes only to selected ones of the processing nodes with reference to probe filtering information representative of states associated with selected ones of the cache memories.
- 16. A probe filtering unit for use in a computer system comprising a plurality of processing nodes interconnected by a first point-to-point architecture, each processing node having a cache memory associated therewith, the probe filtering unit being operable to receive probes corresponding to memory lines from the processing nodes and to transmit the probes only to selected ones of the processing nodes with reference to probe filtering information representative of states associated with selected ones of the cache memories.
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25. A computer implemented method for reducing probe traffic in a computer system comprising a plurality of processing nodes interconnected by a first point-to-point architecture, each processing node having a cache memory associated therewith, the method comprising:
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transmitting a probe from a first one of the processing nodes only to a probe filtering unit, the probe corresponding to a memory line; evaluating the probe with the probe filtering unit to determine whether a valid copy of the memory line is in any of the cache memories, the evaluating being done with reference to probe filtering information associated with the probe filtering unit and representative of states associated with selected ones of the cache memories; transmitting the probe from the probe filtering unit only to selected ones of the processing nodes identified by the evaluating; accumulating probe responses from the selected processing nodes with the probe filtering unit; and responding to the probe from the first processing node only with the probe filtering unit.
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Specification
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- Resources
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Current AssigneeSanmina-SCI Corporation
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Original AssigneeNewisys, Inc. (Sanmina-SCI Corporation)
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InventorsMorton, Eric, Glasco, David B., Khaleel, Adnan, Kota, Rajesh
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Primary Examiner(s)Peugh, Brian R.
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Application NumberUS10/966,161Publication NumberTime in Patent Office1,124 DaysField of Search711/141, 711/148, 711/131, 711/144, 711/145, 711/146, 709/206, 709/213, 709/216, 709/217, 709/218, 709/219US Class Current711/148CPC Class CodesG06F 12/0817 using directory methodsG06F 12/0833 in combination with broadca...G06F 2212/1024 Latency reductionG06F 2212/1041 Resource optimizationG06F 2212/1048 Scalability
