Scheme and method for testing Analog-to-Digital converters
DC
First Claim
1. A method for testing an analog-to-digital converter (ADC), which comprises the steps of:
- inputting a test trigger signal, system clock pulses, and a power source;
integrating the system clock pulses to provide a step-ramp signal;
inputting the step-ramp signal to the ADC under test;
outputting digital output codes of the ADC under test and a reference counter that counts the system clock pulses as the step-ramp signal increases;
comparing output codes of the ADC under test and the reference counter; and
outputting the compared results.
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Abstract
The invention provides a test scheme of analog-to-digital converters and method thereof. It comprises: a control circuit, a step-ramp signal generator, a multiplexer, an n+m-bit counter, and a test analyzing circuit, wherein m=1, 2, 3 . . . , based on desired accuracy of the test scheme. A clock pulse is coupled to the n+m-bit counter and a control circuit for regulating duty cycle, amplitude, and frequency. It is also coupled to a step-ramp signal generating circuit for being integrated as a test signal source. Therefore the step-ramp signal can synchronize with the n+m-bit counter, and the output codes are applied to compare with output codes of the n-bit ADCs for completely digitally analyzing ADC'"'"'s parameters. The step-ramp signal is divided into several segments, each is integrated by the regulated clock signal with different duty cycles, which increases integrating time to compensate leakage currents of the capacitor and improve linearity of the step-ramp signal.
27 Citations
9 Claims
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1. A method for testing an analog-to-digital converter (ADC), which comprises the steps of:
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inputting a test trigger signal, system clock pulses, and a power source; integrating the system clock pulses to provide a step-ramp signal; inputting the step-ramp signal to the ADC under test; outputting digital output codes of the ADC under test and a reference counter that counts the system clock pulses as the step-ramp signal increases; comparing output codes of the ADC under test and the reference counter; and outputting the compared results. - View Dependent Claims (2, 3, 4)
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5. An apparatus for testing an n-bit analog-to-digital converter, compnsing:
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a control circuit, which adjusts the frequency, amplitude, and duty cycle of system clock pulses; a test signal generator, which contains an integrator that receives the system clock pulses from the control circuit to generate a step-ramp signal; a multiplexer, which is controlled by a test trigger signal to choose either a normal signal or a test stimulus; an n+m-bit counter that counts the system clock pulses, as the step-ramp signal increases, the n+n-bit counter having output codes that are synchronous with the step-ramp signal and serving as a reference signal generator when analyzing parameters of the n-bit analog-to-digital converter; and a test response analyzer, which analyzes the output codes of the n-bit analog-to-digital converter and the n+m-bit counter. - View Dependent Claims (6, 7, 8, 9)
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Specification
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- Resources
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Current AssigneeNational Cheng KUNG University (Government of The Republic of China)
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Original AssigneeNational Cheng KUNG University (Government of The Republic of China)
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InventorsWen, Yun-Che
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Primary Examiner(s)Barnie, Rexford
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Assistant Examiner(s)NGUYEN, KHAI M
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Application NumberUS11/168,543Publication NumberTime in Patent Office545 DaysField of Search341/120, 341/155US Class Current341/120CPC Class CodesH03M 1/109 for dc performance, i.e. st...H03M 1/1095 for ac performance, i.e. dy...H03M 1/12 Analogue/digital converters...
